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| description the 3874 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 3874 group includes data link layer communication control cir- cuit, a-d converters, d-a converter, automatic data transfer serial i/o, uart, and watchdog timer etc. the various microcomputers in the 3874 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. for details on availability of microcomputers in the 3874 group, re- fer to the section on group expansion. features l basic machine-language instructions ...................................... 71 l minimum instruction execution time ................................. 0.32 m s (at 6.4 mhz oscillation frequency, in double-speed mode) l memory size rom ............................................................... 16 k to 60 k bytes ram ............................................................... 1024 to 2048 bytes l programmable input/output ports ............................................ 72 l input port .................................................................................... 1 l interrupts ................................................. 27 sources, 16 vectors (interrupt source discrimination register exists, included key in- put interrupt) l timer 1, timer 2, timer 3 ................................................. 8-bit 5 3 l timer x, timer y ............................................................ 16-bit 5 2 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l serial i/o1 .................... 8-bit 5 1(uart or clock-synchronized) l serial i/o2 ................................... 8-bit 5 1(clock-synchronized) l serial i/o3 ...................................................................... 8-bit 5 1 (clock-synchronized automatic data transfer/arbitrary bit trans- fer function available) l a-d converter ................................................. 8-bit 5 8 channels l d-a converter ................................................... 8-bit 5 1 channel l data link layer communication control circuit ............................ 1 l clock generating circuit ..................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) l watchdog timer ............................................................ 20-bit 5 1 l power source voltage ................................................ 3.0 to 5.5 v l power dissipation in double-speed mode ...................................................... 90 mw in high-speed mode .......................................................... 60 mw (at 32 khz oscillation frequency, at 5 v power source voltage) in low-speed mode .......................................................... 180 m w (at 32 khz oscillation frequency, at 3 v power source voltage) l operating temperature range .................................... C40 to 85c (extended operating temperature version and automotive ver- sion) application automotive comfort control for audio system, air conditioning etc., automotive body electronics control, household appliances, and other consumer applications, etc.
2 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers package type : 80p6s-a pin configuration (top view) fig. 1 m38747mct-xxxgp pin configuration pin configuration p8 2 /s out3 p8 3 /s in3 p8 4 /s clk3 p8 5 /s rdy3 p8 6 /s busy3 p8 7 /s stb3 1 2 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p7 7 / adt p7 6 /bus in p7 5 /bus out p7 4 p7 2 /s clk2 p7 1 /s out2 p7 0 /s in2 p5 7 /rtp 1 p5 0 /t out p4 6 /s clk1 p4 5 /t x d p4 4 /r x d p4 3 /int 2 p7 3 p5 1 /int 3 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /int 5 p5 2 /int 4 p5 6 /rtp 0 p4 7 /s rdy1 p3 4 p3 5 p3 0 p3 1 p0 0 p0 3 p0 4 p0 5 p0 6 p0 7 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p1 0 p0 1 p0 2 p3 2 p3 3 p3 6 p3 7 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 av ss p6 7 /an 7 v ref v cc p8 0 /da p8 1 p4 2 /int 1 p9 7 /int 0 x in x out v ss p2 7 /kw 7 p2 6 /kw 6 p2 5 /kw 5 p2 4 /kw 4 p2 3 /kw 3 p2 2 /kw 2 p2 1 /kw 1 p2 0 /kw 0 reset p4 0 /x cout p4 1 /x cin m38747mct-xxxgp 3 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers package type : 80d0 pin configuration (top view) fig. 2 m38749effs pin configuration p8 7 /s stb3 65 p3 0 64 p3 1 63 62 61 p3 4 60 p3 5 59 58 57 p0 0 56 p0 1 55 p0 2 54 p0 3 53 p0 4 52 p0 5 51 p0 6 50 p0 7 49 p1 0 48 p1 1 47 p1 2 46 p1 3 45 p1 4 44 p1 5 43 p1 6 42 p1 7 41 p2 0 /kw 0 40 p8 6 /s busy3 66 p2 1 /kw 1 39 p8 5 /s rdy3 67 p2 2 /kw 2 38 p8 4 /s clk3 68 p2 3 /kw 3 37 p8 3 /s in3 69 p2 4 /kw 4 36 p8 2 /s out3 70 p2 5 /kw 5 35 p8 1 71 p2 6 /kw 6 34 p8 0 /da 72 p2 7 /kw 7 33 v cc 73 v ss 32 v ref 74 x out 31 av ss 75 x in 30 p6 7 /an 7 76 p4 0 /x cou t 29 p6 6 /an 6 77 p4 1 /x cin 28 p6 5 /an 5 78 27 p6 4 /an 4 79 p9 7 /int 0 26 p6 3 /an 3 80 p4 2 /int 1 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p7 7 /adt p7 4 p7 3 p7 2 /s clk2 p7 1 /s out2 p7 0 /s in2 p5 7 /rtp 1 p5 6 /rtp 0 p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /int 5 p5 2 /int 4 p5 1 /int 3 p5 0 /t out p4 6 /s clk1 p4 5 /txd p4 4 /rxd p4 3 /int 2 24 p7 6 /bus in p7 5 /bus out reset p4 7 /s rdy1 p3 2 p3 3 p3 6 p3 7 4 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional block diagram (package : 80p6s-a) fig. 3 functional block diagram functional block key-on wake-up t out int 0 adt reset data bus c p u a x y s pc h pc l ps reset v cc v ss reset input ( 5 v ) ( 0 v ) r o m r a m 25 71 30 i/o port p5 p4(8) i/o port p4 i/o port p2 p2(8) i/o port p0 p0(8) i/o port p1 p1(8) i/o port p3 p3(8) i/o port p6 p5(8) i/o port p9 p9(1) 47 48 49 50 51 52 53 54 39 40 41 42 43 44 45 46 31 32 33 34 35 36 37 38 55 56 57 58 59 60 61 62 18 19 20 21 22 23 26 24 17 10 11 12 13 14 15 16 p6(8) 27 clock generating circuit x in out x main-clock input main-clock output cout x x cin sub-clock output sub-clock input serial i/o1(8) timer x(16) timer y(16) timer 1(8) timer 2(8) timer 3(8) f 28 29 74 75 76 77 78 79 80 1 i/o port p7 p7(8) 234567 9 8 i/o port p8 p8(8) 63 64 65 66 67 68 69 70 72 73 v ref av ss x cin cout x int 2 ,int 1 int 5 ,int 4, int 3 rtp 1 ,rtp 0 cntr 1 ,cntr 0 a-d converter (8) bus in ,bus out serial i/o3 automatic transfer controller serial i/o3 automatic transfer ram local data bus watchdog timer reset d-a converter (8) serial i/o2(8) data link layer communication control circuit 5 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers v cc , v ss pin description functions name pin ?apply voltage of 3.0 v C 5.5 v to vcc, and 0 v to vss. ?reference voltage input pin for a-d and d-a converters. ?analog power source input pin for a-d and d-a converters. ?connect to v ss . ?reset input pin for active l. ?input and output pins for the clock generating circuit. ?connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ?when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ?feedback resistor is built in between x in pin and x out pin. ?8-bit cmos i/o port. ?i/o direction register allows each pin to be individually programmed as either input or output. ?cmos compatible input level. ?cmos 3-state output structure. ?8-bit i/o port with the same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. power source input table 1 pin description (1) function except a port function reference voltage input analog power source input clock input clock output i/o port p0 i/o port p1 i/o port p2 i/o port p3 v ref av ss reset reset input x in x out p0 0 Cp0 7 p1 0 Cp1 7 p2 0 Cp2 7 p3 0 Cp3 7 ?sub-clock generating circuit i/o pins connect a resonator. (this circuit cannot be operated by an external clock.) ?interrupt input pins p4 0 /x cout , p4 1 /x cin p4 2 /int 1 , p4 3 /int 2 p4 4 /r x d, p4 5 /t x d, p4 6 /s clk1 , p4 7 /s rdy1 p5 0 /t out p5 1 /int 3 C p5 3 /int 5 p5 4 /cntr 0 , p5 5 /cntr 1 p5 6 /rtp 0 , p5 7 /rtp 1 ?serial i/o1 function pins ?timer 2 output pin ?interrupt input pins ?timer x, timer y function pins ?real time port function pins i/o port p4 i/o port p5 ?8-bit i/o port with the same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. 6 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functions name pin function except a port function table 2 pin description (2) p6 0 /an 0 C p6 7 /an 7 p7 0 /s in2 , p7 1 /s out2 , p7 2 /s clk2 i/o port p6 i/o port p7 i/o port p8 ?8-bit i/o port with the same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. ?8-bit i/o port with the same function as port p0. ?cmos compatible input level. ?cmos 3-state output structure. ?a-d converter input pins ?serial i/o2 function pins ?serial i/o3 function pins p7 3 , p7 4 p7 5 /bus out , p7 6 /bus in p7 7 /adt p8 0 /da p8 1 p8 2 /s out3 , p8 3 /s in3 , p8 4 /s clk3 , p8 5 /s rdy3 p8 6 /s busy3 , p8 7 /s stb3 ?data link layer communication con- trol pins ?a-d trigger input pin ?d-a converter output pin ?8-bit i/o port with the same function as port p0. ?1-bit input port. ?cmos compatible input level. input port p9 ?interrupt input pin p9 7 /int 0 7 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers part numbering fig. 4 part numbering m3874 7 m c t- xxx gp product package type gp : 80p6s-a fs : 80d0 rom number omitted in some types. rom/prom size 4 5 6 7 8 9 : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used. memory type m e : mask rom version : eprom or one time prom version ram size 7 8 9 : 1024 bytes : 1536 bytes : 2048 bytes d : extended operating temperature version f : extended operating speed version of ? t : automotive version a b c d e f 8 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 5 main clock input oscillation frequency in double-speed mode 3874 group main clock input oscillation frequency in double-speed mode 6.4 mhz 5 mhz 4.0 v 4.5 v 5.5 v ?eprom or one time prom version main clock input oscillation frequency f(x in ) (mhz) power source voltage v cc (v) 6.4 mhz 4.0 v 5.5 v ?mask rom version main clock input oscillation frequency f(x in ) (mhz) power source voltage v cc (v) in low-speed mode, middle-speed mode, and high-speed mode, characteristic of main clock input oscillation frequency guarantee limit is not different. 9 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers group expansion (extended operating temperature version) the 3874 group (extended operating temperature version) is de- signed for automotive comfort and amusement control such as audio, air-conditioner etc., household appliances, and other con- sumer applications. mitsubishi plans to expand the 3874 group (extended operating temperature version) as follows: memory type support for mask rom, one time prom, and eprom versions memory size rom/prom size ............................................... 48 k to 60 k bytes ram size .......................................................... 1024 to 2048 bytes packages 80p6s-a .................................. 0.65 mm-pitch plastic molded qfp 80d0 ....................... 0.8 mm-pitch ceramic lcc (eprom version) fig. 6 memory expansion plan (extended operating temperature version) currently planning products are listed below. ram size (bytes) remarks package table 3 support products product name as of march 1998 61440 (61310) 49152 (49022) (p) rom size (bytes) rom size for user in ( ) memory expansion plan of 3874 group (extended operating temperature version) products under development or planning : the development schedule and specification may be revised without notice. planning products may be stopped during the development. m38749efdgp m38749effs m38749mff m38747mcf 2048 80p6s-a 80d0 one time prom version (blank) 1024 80p6s-a eprom version (for software development, operat- ing temperature = C20 to 85c) mask rom version 32k 1024 60k rom size (bytes) ram size (byte) 1536 2048 36k 40k 44k 48k 52k 56k 28k 24k 16k 20k mass product mass product m38749mff/efd m38747mcf 10 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers group expansion (automotive version) the 3874 group (automotive version) is designed for automotive body electronics control. mitsubishi plans to expand the 3874 group (automotive version) as follows: memory type support for mask rom and one time prom versions memory size rom/prom size ............................................... 16 k to 60 k bytes ram size .......................................................... 1024 to 2048 bytes packages 80p6s-a .................................. 0.65 mm-pitch plastic molded qfp fig. 7 memory expansion plan (automotive correspondence version) currently planning products are listed below. ram size (bytes) remarks package table 4 support products product name as of march 1998 61440 (61310) 49152 (49022) 24576 (24446) 16384 (16254) (p) rom size (bytes) rom size for user in ( ) memory expansion plan of 3874 group (automotive version) products under development or planning : the development schedule and specification may be revised without notice. planning products may be stopped during the development. m38749eft m38747mct m38747m6t m38747m4t 80p6s-a one time prom version mask rom version 2048 1048 32k 1024 60k rom size (byte) ram size (byte) 1536 2048 36k 40k 44k 48k 52k 56k 28k 24k 16k 20k mass product m38747mct mass product m38749eft mass product m38747m6t mass product m38747m4t *supported only prom version shipped after writing 11 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers functional description central processing unit (cpu) the 3874 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit etc. the cpu mode register is allocated at address 003b 16 . fig. 8 structure of cpu mode register cpu mode register ( cpum : address 003b 16 ) b7 b0 stack page selection bit 0 : page 0 1 : page 1 x cout drivability selection bit 0 : low drive 1 : high drive processor mode bits b1 b0 0 0 : single-chip mode 0 1 : 1 0 : not available 1 1 : port x c switch bit 0 : i/o port function 1 : x cin ? cout oscillating function main clock (x in ? out ) stop bit 0 : oscillating 1 : stopped main clock division ratio selection bits b7 b6 0 0 : f = f(x in )/2 (high-speed mode) 0 1 : f = f(x in )/8 (middle-speed mode) 1 0 : f = f(x cin )/2 (low-speed mode) 1 1 : f = f(x in ) (double-speed mode) note: when setting b7 to b3, refer to notes of figure 71. 12 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. fig. 9 memory map diagram 0100 16 0000 16 0040 16 ff00 16 ffdc 16 fffe 16 ffff 16 1024 1536 2048 xxxx 16 043f 16 063f 16 083f 16 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 yyyy 16 zzzz 16 ram rom 0200 16 0300 16 sfr area not used interrupt vector area rom area reserved rom area (128 bytes) zero page special page ram area ram size (bytes) address xxxx 16 rom size (bytes) address yyyy 16 reserved rom area address zzzz 16 serial i/o3 automatic transfer ram area 13 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 10 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 serial i/o2 register (sio2) port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p7 (p7) port p7 direction register (p7d) port p8 (p8) port p8 direction register (p8d) transmit/receive buffer register (tb/rb) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart control register (uartcon) baud rate generator (brg) serial i/o2 control register (sio2con) interrupt control register 2 (icon2) a-d/d-a conversion register (ad) timer 3 (t3) timer x mode register (txm) a-d control register (adcon) interrupt source discrimination register 2 (ireqd2) interrupt source discrimination control register 2 (icond2) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) timer x (low-order) (txl) timer y (low-order) (tyl) timer 1 (t1) timer 2 (t2) timer x (high-order) (txh) timer y (high-order) (tyh) port p9 (p9) serial i/o3 register/transfer counter (sio3) serial i/o3 control register 1 (sio3con1) serial i/o3 control register 2 (sio3con2) serial i/o3 control register 3 (sio3con3) serial i/o3 automatic transfer data pointer (sio3dp) timer y mode register (tym) timer 123 mode register (t123m) communication mode register (busm) transmit control register (txdcon) transmit status register (txdsts) receive control register (rxdcon) receive status register (rxdsts) bus interrupt source discrimination control register (bicond) control field selection register (cfsel) control field register (cf) transmit/receive fifo (trfifo) pull up register (pullu) interrupt source discrimination register 1 (ireqd1) interrupt source discrimination control register 1 (icond1) watchdog timer control register (wdtcon) 14 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers p3 0 Cp3 7 pin name input/output i/o structure non-port function ref.no. table 5 i/o port function (1) related sfrs i/o ports the i/o ports p0Cp8 have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, and each pin can be set to be in- put port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin becomes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. p0 0 Cp0 7 port p0 input/output, individual bits ?cmos compatible input level ?cmos 3-state output ?key input (key-on wake-up) interrupt in- put ?pull up register (1) (2) ?cmos compatible input level ?cmos 3-state output ?cmos compatible input level ?cmos 3-state output ?cmos compatible input level ?cmos 3-state output ?cmos compatible input level ?cmos 3-state output ?cmos compatible input level ?cmos 3-state output ?cmos compatible input level ?cmos 3-state output input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits input/output, individual bits por t p1 port p2 port p3 port p4 por t p5 port p6 p1 0 Cp1 7 p2 0 Cp2 7 p4 0 /x cout p4 1 /x cin p4 2 /int 1, p4 3 /int 2 ?sub-clock generating circuit i/o ?external interrupt input ?serial i/o1 function i/o ?cpu mode register ?cpu mode register ?interrupt edge selection register ?serial i/o1 control reg- ister ?serial i/o1 status regis- ter ?uart control register ?pull up register p4 4 /r x d p4 5 /t x d p4 6 /s clk1 ?timer 123 mode regis- ter ?timer 2 output p5 0 /t out p5 1 /int 3 , p5 2 /int 4 , p5 3 /int 5 p5 4 /cntr 0 p5 5 /cntr 1 p5 6 /rtp 0 p5 7 /rtp 1 ?external interrupt input ?interrupt edge selection register ?timer x function i/o ?timer x mode register ?timer y function i/o ?real time port function output ?real time port function output ?a-d converter input ?timer y mode register ?timer x mode register ?timer y mode register (1) (3) (4) (5) (6) (7) (8) (9) (10) (5) (11) (12) (13) (14) ?a-d control register p6 0 /an 0 C p6 7 /an 7 p4 7 /s rdy1 15 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers note: make sure that the input level at each pin is either 0 v or vcc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from vcc to vss through the input-stage gate. pin name input/output i/o function non-port function ref.no. table 6 i/o port function (2) related sfrs p7 0 /s in2 p7 1 /s out2 p7 5 /bus out p7 6 /bus in p7 7 /adt p8 0 /da p8 1 por t p7 port p8 port p9 input/output, individual bits ?cmos compatible input level ?cmos 3-state output ?serial i/o2 function i/o ?serial i/o2 control reg- ister ?pull up register (15) (16) (17) (1) (18) (19) (20) (21) (1) (22) p7 2 /s clk2 p7 3 ,p7 4 ?data link layer commu- nication control i/o ?a-d trigger input ?d-a function output ?serial i/o3 function i/o ?external interrupt input ?communication mode register ?transmit control regis- ter ?transmit status register ?receive control regiser ?receive status register ?bus interrupt source discrimination control register ?control field selection register ?control field register ?transmit/receive fifo ?a-d control register ?a-d control register ?serial i/o3 register/ transfer counter ?serial i/o3 control reg- ister 1 ?serial i/o3 control reg- ister 2 ?serial i/o3 control reg- ister 3 ?serial i/o3 automatic transfer data pointer ?interrupt edge selection register input/output, individual bits (23) (24) (25) (26) (27) (28) input ?cmos compatible in- put level ?cmos 3-state output ?cmos compatible input level p8 2 /s out3 p8 3 /s in3 p8 4 /s clk3 p8 5 /s rdy3 p8 6 /s busy3 p8 7 /s stb3 p9 7 /int 0 16 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers pull-up control p2 0 Cp2 6 , t x d, s clk1 , s out2, and s clk2 can perform pull-up con- trol by setting 1 to the pull-up register (address 0033 16 ). p2 0 Cp2 7 s pull-up is valid in the input mode, and t x d, s clk1 , s out2, and s clk2 s pull-up is valid in the output mode. fig.11 structure of pull-up register 0: no pull-up 1: pull-up pull-up register (pullu : address 0033 16 ) p2 6 , p2 7 pull-up p2 5 pull-up p2 2 ?2 4 pull-up p2 0 , p2 1 pull-up t x d, s clk1 pull-up s out2 , s clk2 pull-up not used (returns ??when read) (do not write ??to these bits.) b7 b0 17 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 12 port block diagram (1) (1) ports p0,p1,p3,p7 3 ,p7 4 ,p8 1 direction register data bus port latch (2) port p2 (3) port p4 0 data bus port x c switch bit port latch oscillator port p4 1 port x c switch bit (4) port p4 1 data bus port x c switch bit port latch sub-clock generating circuit input (5) ports p4 2 ,p4 3 ,p5 1 ,p5 2 ,p5 3 data bus direction register port latch int 1 ?nt 5 interrupt input data bus direction register port latch key input interrupt input p2 pull-up (6) port p4 4 direction register data bus serial i/o1 enable bit receive enable bit serial i/o1 input port latch direction register direction register 18 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 13 port block diagram (2) serial i/o1 mode selection bit serial i/o1 enable bit s rdy1 output enable bit (9) port p4 7 data bus serial i/o1 ready output port latch (10) port p5 0 port latch data bus t out output control bit timer output (11) port p5 4 (12) port p5 5 port latch data bus pulse output mode timer output cntr 0 interrupt input event count input pulse width measurement gate input (7) port p4 5 data bus p4 5 /t x d p-channel output disable bit serial i/o1 enable bit transmit enable bit serial i/o1 output port latch t x d pull-up cntr 1 interrupt input event count input reload input data bus port latch (8) port p4 6 serial i/o1 enable bit serial i/o1 synchronous clock selection bit data bus serial i/o1 clock output serial i/o1 clock input port latch s clk1 pull-up serial i/o1 mode selection bit serial i/o1 enable bit direction register direction register direction register direction register direction register direction register 19 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 14 port block diagram (3) data bus port latch real time port control bit data for real time port (13) ports p5 6, p5 7 (14) port p6 (16) port p7 1 s out2 pin selection bit serial i/o2 output p-channel output disable bit s out2 output control bit s clk2 pin selection bit s out2 output signal in operating s out2 pull-up (15) port p7 0 serial i/o2 input data bus port latch analog input pin selection bit a-d converter input direction register data bus port latch direction register direction register data bus port latch direction register 20 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 15 port block diagram (4) (17) port p7 2 serial i/o2 clock output serial i/o2 clock input s clk2 pin selection bit p7 1 /s out2 ?p7 2 /s clk2 p-channel output disable bit s clk2 pull-up (18) port p7 5 (19) port p7 6 (20) port p7 7 adt interrupt input when the direction register is ?,?the schmidt input pin is connected to port. (21) port p8 0 d-a converter output d-a on data link layer communication control circuit valid signal (output from sub-cpu) data link layer communication control circuit transmit output data link layer communication control circuit valid signal (output from sub-cpu) data link layer communication control circuit receive input data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register 21 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 16 port block diagram (5) (22) port p8 2 serial transfer selection bit serial i/o disabled serial i/o3 output p8 2 /s out3 ?p8 4 /s clk3 p-channel output disable bit s out3 output control bit (23) port p8 3 transfer mode selection bit serial transfer selection bit serial i/o disabled serial i/o3 input serial i/o3 ready output serial i/o3 ready input (25) port p8 5 serial transfer selection bit serial i/o disabled p8 5 /s rdy3 ?p8 6 /s busy3 pin control bit s rdy3 input p8 5 /s rdy3 ?p8 6 /s busy3 pin control bit s rdy3 output (26) port p8 6 p8 5 /s rdy3 ?p8 6 /s busy3 pin control bit s busy3 input serial i/o3 busy output serial i/o3 busy input serial transfer selection bit serial i/o disabled p8 5 /s rdy3 ?p8 6 /s busy3 pin control bit s busy3 output (27) port p8 7 serial i/o disabled serial i/o3 synchronous clock selection bit s stb3 ,s stb3 output (24) port p8 4 serial transfer selection bit serial i/o disabled serial i/o3 synchronous clock selection bit internal synchronous clock serial i/o3 clock output serial i/o3 clock input p8 2 /s out3 ?p8 4 /s clk3 p-channel output disable bit data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register data bus port latch direction register 22 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 17 port block diagram (6) (28) port p9 7 data bus int 0 interrupt input 23 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers interrupts interrupts occur by 27 sources: 10 external, 16 internal, and 1 soft- ware. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the in- terrupt disable flag is 0. interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i (interrupt disable) flag disables all interrupts except the brk in- struction interrupt. the interrupt control circuit consists of two types of interrupts: one factor/one vector interrupt and multiple factors/one vector inter- rupt. the configuration is shown in figure 18. interrupt operation when an interrupt occurs, the following operations are automati- cally performed: 1. the contents of the program counter and the processor status register are pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit for each vector is cleared. (the corresponding inter- rupt request bit for each interrupt factor is not cleared.) 3. the interrupt jump destination address of interrupt which has the highest priority is loaded to the program counter. interrupt factor determination the interrupt request bit for each vector of multiple factors/one vector interrupt is set to 1 when the interrupt disable flag (i) is 0 and one of the factor interrupt enable bits is 1 and the corre- sponding factor interrupt request bit changes from 0 to 1. at this time, if the vector interrupt enable bit is 1, the interrupt oc- curs. (note that the interrupt request bit for each vector and the factor interrupt request bit are both edge sense.) when 2 or more interrupt requests of interrupt factors assigned to one interrupt vector are generated at the same time, confirm the interrupt request bits for each interrupt factor assigned to the vec- tor, and process according to the priority. if the interrupt request bit for the interrupt factor is 1 and the in- terrupt enable bits for interrupt factor and each vector are both 1; for example, when an interrupt of another interrupt factor assigned to the same vector occurs while an interrupt processing routine is executed, the interrupt occurs again after returning. clear the in- terrupt request bits which are not necessary or which have been already processed before executing the interrupt flag clear (cli) or interrupt processing routine return (rti) instruction. the interrupt request bits for each interrupt factor are not cleared by hardware after an interrupt vector address branching. clear these bits by software in the interrupt processing routine. use the ldm, sta, etc. instructions to do it. do not use the read- modify- write instruction; for example, the clb. n notes when the active edge of an external interrupt (int 0 Cint 5 , cntr 0 , cntr 1 ) is set, the corresponding interrupt request bit may also be set. therefore, take following sequence: (1) disable the external interrupt which is selected. (2) change the active edge in interrupt edge selection register (in case of cntr 0 : timer x mode register; in case of cntr 1 : timer y mode register). (3) clear the set interrupt request bit to 0. (4) enable the external interrupt which is selected. 24 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers int 0 int 1 receive bus interrupt source 1 receive bus interrupt source 2 receive bus interrupt source 3 transmit bus interrupt source 1 transmit bus interrupt source 2 transmit bus interrupt source 3 timer x timer y timer 2 timer 3 int 2 serial i/o3 interrupt cntr 0 cntr 1 timer 1 int 3 int 4 int 5 adt a-d converter serial i/o2 interrupt key input (key- on wake-up) serial i/o1 receive serial i/o1 transmit brk instruction interrupt request generating conditions remarks interrupt sources low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 table 7 interrupt vector addresses and priority notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. 3: either adt interrupt or a-d converter interrupt can be used. both adt interrupt and a-d converter interrupt cannot be used. vector addresses (note 1) reset (note 2) at reset at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input when receive bus interrupt source 1 request bit becomes 1 from 0 non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) the condition which the receive bus interrupt factor request bit becomes 1 is defined according to each communication protocol specification confirmation. the condition which the transmit bus interrupt factor request bit becomes 1 is defined according to each communication protocol specification confirmation. external interrupt (active edge selectable) valid only when serial i/o3 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) valid only when adt interrupt is selected external interrupt (falling valid) valid only when a-d converter interrupt is selected valid only when serial i/o2 is selected external interrupt (falling valid) valid only when serial i/o1 is selected valid only when serial i/o1 is selected non-maskable software interrupt when receive bus interrupt source 2 request bit becomes 1 from 0 when receive bus interrupt source 3 request bit becomes 1 from 0 when transmit bus interrupt source 1 request bit becomes 1 from 0 when transmit bus interrupt source 2 request bit becomes 1 from 0 when transmit bus interrupt source 3 request bit becomes 1 from 0 at timer x underflow at timer y underflow at timer 2 underflow at timer 3 underflow at detection of either rising or falling edge of int 2 input at completion of serial i/o3 data transmission/reception at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at timer 1 underflow at detection of either rising or falling edge of int 3 input at detection of either rising or falling edge of int 4 input at detection of either rising or falling edge of int 5 input at falling of adt pin input at completion of a-d converter at completion of serial i/o2 data transmission/reception at falling of port p2 0 to p2 5 (at input) input logical level and at completion of serial i/o1 data reception at completion of serial i/o1 transmission shift or when transmission buffer is empty at brk instruction execution 25 3874 gr oup single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig.18 interrupt control diagram interrupt enable bit for interrupt factor interrupt request bit for interrupt factor interrupt disable flag (i) interrupt occurrence brk instruction reset interrupt disable flag (i) clear instruction by user program interrupt request from multiple factors: idreq y interrupt request ireqin x interrupt request bit for each vector: ireq x d q r t clear instruction by user program sync stp instruction q interrupt request of interrupt factor: idreqin yz r t d interrupt request bit for each vector: ireq y interrupt enable bit for each vector hardware clear signal by occurrence of interrupt clear instruction by user program q r t d q r t d interrupt request get control signal: ireqget interrupt enable bit for each vector hardware clear signal by occurrence of interrupt clear instruction by user program q r t d q r t d interrupt request get control signal: ireqget multiple factors/one vector interrupt one factor/one vector interrupt internal system clock f 26 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timing to interrupt request acceptance the cycle number of internal system clock required from occur- rence to acceptance of an interrupt request depends on the type of interrupt: multiple factors/one vector or one factor/one vec- tor. for one factor/one vector interrupt, the cpu starts processing the management after interrupt acceptance at the next instruction execution timing (rising edge of sync signal) immediately after the interrupt request is generated. for multiple factors/one vector interrupt, the cpu starts processing the management after inter- rupt acceptance at the second instruction execution timing (rising edge of sync signal) after the interrupt request for interrupt factor determination is generated. in other words, multiple factors/one vector interrupt required one instruction execution cycle number (2 to 16 cycles of internal system clock) more than that of one factor/one vector interrupt to begin the interrupt sequence. figure 18 shows the interrupt control diagram and figure 19 shows the timing from occurrence to acceptance of interrupt request. for one factor/one vector interrupt, the interrupt request is gen- erated at timing (a) and the processing after acceptance begins at timing (b). for multiple factors/one vector interrupt, the inter- rupt factor determination request is generated at timing (c), the interrupt request is generated at timing (d), and the processing after acceptance begins at timing (e). 27 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig.19 timing from occurrence to acceptance of interrupt not used irget irget (c) internal system clock f address bus data bus sync interrupt source determination request signal input idreqin y interrupt request signal from interrupt source idreq y pc not used (d) management after interrupt acceptance (e) interrupt request signal ireq y internal system clock f address bus data bus sync interrupt request signal ireqx pc (b) management after interrupt acceptance (a) interrupt request signal input ireqinx s,sps s-1,sps s-2,sps pc h pc l ps (a) one factor/one vector interrupt (b) multiple factors/one vector interrupt 2 to 16 cycles of f 28 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 20 structure of interrupt-related registers b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 interrupt edge selection register int 0 active edge selection bit int 1 active edge selection bit int 2 active edge selection bit int 3 active edge selection bit int 4 active edge selection bit int 5 active edge selection bit not used (returns 0 when read) (intedge : address 003a 16 ) interrupt request register 1 int 0 interrupt request bit int 1 interrupt request bit receive bus interrupt request bit transmit bus interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 2 interrupt request bit timer 3 interrupt request bit interrupt control register 1 int 0 interrupt enable bit int 1 interrupt enable bit receive bus interrupt enable bit transmit bus interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 2 interrupt enable bit timer 3 interrupt enable bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 ) (icon1 : address 003e 16 ) interrupt request register 2 int 2 interrupt request bit cntr 0 , serial i/o3 interrupt request bit cntr 1 interrupt request bit timer 1 interrupt request bit int 3 , int 4 , int 5 interrupt request bit adt/a-d converter, serial i/o2 interrupt request bit key input, serial i/o1 receive, serial i/o1 transmit interrupt request bit not used (returns 0 when read) (ireq2 : address 003d 16 ) interrupt control register 2 int 2 interrupt enable bit cntr 0 , serial i/o3 interrupt enable bit cntr 1 interrupt enable bit timer 1 interrupt enable bit int 3 , int 4 , int 5 interrupt enable bit adt/a-d converter, serial i/o2 interrupt enable bit key input, serial i/o1 receive, serial i/o1 transmit interrupt enable bit not used (returns 0 when read) (do not write 1 to this bit) 0 : interrupts disabled 1 : interrupts enabled (icon2 : address 003f 16 ) 0 : falling edge active 1 : rising edge active interrupt source discrimination register 1 int 3 interrupt request bit int 4 interrupt request bit int 5 interrupt request bit serial i/o1 receive interrupt request bit serial i/o1 transmit interrupt request bit key input interrupt request bit serial i/o2 interrupt request bit atd/a-d converter interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued (ireqd1 : address 0038 16 ) interrupt source discrimination control register 1 int 3 interrupt enable bit int 4 interrupt enable bit int 5 interrupt enable bit serial i/o1 receive interrupt enable bit serial i/o1 transmit interrupt enable bit key input interrupt enable bit serial i/o2 interrupt enable bit adt/a-d converter interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled (icond1 : address 0039 16 ) interrupt source discrimination register 2 cntr 0 interrupt request bit serial i/o3 interrupt request bit not used (returns 0 when read) 0 : no interrupt request issued 1 : interrupt request issued (ireqd2 : address 0036 16 ) interrupt source discrimination control register 2 cntr 0 interrupt enable bit serial i/o3 interrupt enable bit not used (return 0 when read) 0 : interrupt disabled 1 : interrupt enabled (icond2 : address 0037 16 ) 0 : no interrupt request issued 1 : interrupt request issued 0 : interrupts disabled 1 : interrupts enabled 29 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers key input interrupt a key input interrupt request is generated by applying l level to any pin of port p2 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0. an example of using a key input interrupt is shown in figure 21, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p2 0 Cp2 4 . fig. 21 connection example when using key input interrupt and port p2 block diagram ] ]] ] ]] ] ]] ] ]] ] ]] ] ]] ] ]] ] ]] port p2 0 latch port p2 0 direction register = ? port p2 1 latch port p2 1 direction register = ? port p2 2 latch port p2 2 direction register = ? port p2 3 latch port p2 3 direction register = ? port p2 4 latch port p2 4 direction register = ? port p2 5 latch port p2 5 direction register = ? port p2 6 latch port p2 6 direction register = ? port p2 7 latch port p2 7 direction register = ? p2 0 input p2 1 input p2 2 input p2 3 input p2 4 input p2 5 output p2 6 output p2 7 output pull up register bit 0 = ? port p2 input reading circuit key input interrupt request port pxx ??level output ] p-channel transistor for pull-up ]] cmos output buffer pull up register bit 1 = ? pull up register bit 2 = ? pull up register bit 3 = ? 30 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timers the 3874 group has five timers: timer x, timer y, timer 1, timer 2, and timer 3. timer x and timer y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. all timers are down count timers. when the timer reaches 00 16 or 0000 16 , an underflow occurs at the next count pulse and the cor- responding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit cor- responding to that timer is set to 1. read and write operation on 16-bit timer must be performed for both high and low-order bytes. when reading a 16-bit timer, read the high-order byte first. when writing to a 16-bit timer, write the low-order byte first. the 16-bit timer cannot perform the correct op- eration when reading during the write operation, or when writing during the read operation. fig. 22 timer block diagram cntr 0 active edge switch bit timer 1 count source selection bit real time port control bit ?? ? p5 5 /cntr 1 ? x in /16 (x cin /16 in f = x cin /2) cntr 1 active edge switch bit ?0 timer y stop control bit falling edge detection period measurement mode timer y interrupt pulse width hl continuously measurement mode rising edge detection ?0??1??1 timer y operating mode bit timer x interrupt timer x mode register write signal p5 4 /cntr 0 q q t s p5 4 direction register pulse output mode p5 4 latch timer x stop control bit ? ? timer x write control bit q d latch q d latch ? ? ? ?0 timer x operat- ing mode bit ?0??1??1 x in /16 (x cin /16 in f = x cin /2) pulse width measurement mode cntr 0 active edge switch bit pulse output mode q q t s ? p5 0 direction register p5 0 latch ? t out output active edge switch bit ? timer 2 write control bit ? ? t out output control bit ? p5 0 /t out x cin timer 3 count source selection bit ? ? timer 2 interrupt timer 3 interrupt t out output control bit timer 2 count source selection bit timer 1 interrupt data bus x in /16 (x cin /16 in f = x cin /2) x in /16 (x cin /16 in f = x cin /2) x in /16(x cin /16 in f = x cin /2) p5 6 direction register ? real time port control bit ? p5 6 /rtp 0 p5 6 latch p5 7 direction register ? real time port control bit ? p5 7 /rtp 1 p5 7 latch p5 6 data for real time port p5 7 data for real time port timer y (low) (8) timer y (high) (8) timer 3 latch (8) timer 3 (8) timer 1 latch (8) timer 1 (8) timer 2 latch (8) timer 2 (8) timer x (low) (8) timer x (high) (8) timer x (low) latch (8) timer x (high) latch (8) timer y (low) latch (8) timer y (high) latch (8) 31 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 23 structure of timer x mode register timer x timer x is a 16-bit timer that can be selected in one of four modes and can be controlled the timer x write and the real time port by setting the timer x mode register. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in system clock f = x cin / 2). (2) pulse output mode each time the timer underflows, a signal output from the cntr 0 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when using a timer in this mode, set the direction register of corresponding port to output mode. (3) event counter mode the timer counts signals input through the cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. (4) pulse width measurement mode the count source is f(x in )/16 (or f(x cin )/16 in system clock f = x cin /2. if cntr 0 active edge switch bit is 0, the timer counts while the input signal of cntr 0 pin is at h. if it is 1, the timer counts while the input signal of cntr 0 pin is at l. n notes l timer x write control if the timer x write control bit is 1, when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. if the timer x write control bit is 0, when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. when the value is to be written in latch only, if the value is written to the latch at timer x underflows, the value is consequently loaded in the timer x and the latch at the same time. unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer x are performed at the same timing. l cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. l real time port control data for the real time port are output from ports p5 6 and p5 7 each time the timer x underflows. (however, if the real time port control bit is changed from 0 to 1, data are output independent of the timer x operation.) when the data for the real time port is changed while the real time port function is valid, the changed data are out- put at the next underflow of timer x. before using this function, set the corresponding port direction registers to output mode. timer x mode register (txm : address 0027 16 ) timer x write control bit 0 : write value in latch and counter 1 : write value in latch only real time port control bit 0 : real time port function invalid 1 : real time port function valid p5 6 data for real time port p5 7 data for real time port timer x operating mode bits b5 b4 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode cntr 0 active edge switch bit 0 : count at rising edge in event counter mode start from ??output in pulse output mode measure ??pulse width in pulse width measurement mode falling edge active for cntr 0 interrupt 1 : count at falling edge in event counter mode start from ??output in pulse output mode measure ??pulse width in pulse width measurement mode rising edge active for cntr 0 interrupt timer x stop control bit 0 : count start 1 : count stop b7 b0 32 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timer y timer y is a 16-bit timer that can be selected in one of four modes. (1) timer mode the timer counts f(x in )/16 (or f(x cin )/16 in system clock f = x cin / 2). (2) period measurement mode cntr 1 interrupt request is generated at rising/falling edge of cntr 1 pin input signal. simultaneously, the value in timer y latch is reloaded in timer y and timer y continues counting down. except for the above-mentioned, the operation in period measurement mode is the same as in timer mode. the timer value just before the reloading at rising/falling of cntr 1 pin input signal is retained until the timer y is read once after the reload. the rising/falling timing of cntr 1 pin input signal is found by cntr 1 interrupt. (3) event counter mode the timer counts signals input through the cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. (4) pulse width hl continuously measure- ment mode cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. n note l cntr 1 interrupt active edge selection cntr 1 interrupt active edge depends on the cntr 1 active edge switch bit. however, in pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. fig. 24 structure of timer y mode register timer y mode register (tym : address 0028 16 ) b7 b0 not used (return ??when read) timer y operating mode bits b5 b4 0 0 : timer mode 0 1 : period measurement mode 1 0 : event counter mode 1 1 : pulse width hl continuously measurement mode cntr 1 active edge switch bit 0 : count at rising edge in event counter mode measure the falling edge to falling edge period in period measurement mode falling edge active for cntr 1 interrupt 1 : count at falling edge in event counter mode measure the rising edge period in period measurement mode rising edge active for cntr 1 interrupt timer y stop control bit 0 : count start 1 : count stop 33 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timer 1, timer 2, timer 3 timer 1, timer 2, and timer 3 are 8-bit timers. the count source for each timer can be selected by timer 123 mode register. l timer 2 write control when the timer 2 write control bit is 1, and the value is written in the address of timer 2, the value is loaded only in the latch. the value in the latch is loaded in timer 2 after timer 2 underflows. when the timer 2 write control bit is 0, and the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. l timer 2 output control an inversion signal from t out pin is output each time timer 2 underflows. in this case, set the port p5 0 direction register to the output mode. n note l timer 1 to timer 3 when the count source of timer 1 to 3 is changed, the timer count- ing value may be changed large because a thin pulse is generated in count input of timer. if timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. fig. 25 structure of timer 123 mode register t out output active edge switch bit 0 : start at ??output 1 : start at ??output t out output control bit 0 : t out output disabled 1 : t out output enabled timer 2 write control bit 0 : write data in latch and counter 1 : write data in latch only timer 2 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 3 count source selection bit 0 : timer 1 output 1 : f(x in )/16 (or f(x cin )/16 in low-speed mode) timer 1 count source selection bit 0 : f(x in )/16 (or f(x cin )/16 in low-speed mode) 1 : f(x cin ) not used (return ??when read) timer 123 mode register (t123m :address 0029 16 ) note : internal clock f is f(x cin )/2 in the low-speed mode. b7 b0 34 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 27 operation of clock synchronous serial i/o1 function serial i/o serial i/o1 serial i/o can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation. fig. 26 block diagram of clock synchronous serial i/o (1) clock synchronous serial i/o1 mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit (b6) of the serial i/o1 control register to 1. for clock synchronous serial i/o1, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register (ad- dress 0018 16 ). p4 6 /s clk1 p4 7 /s rdy1 p4 4 /r x d p4 5 /t x d x in 1/4 1/4 f/f serial i/o1 status register serial i/o1 control register receive buffer register (rb) address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) clock control circuit shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator address 001c 16 brg count source selection bit clock control circuit falling-edge detector data bus address 0018 16 shift clock transmit shift register shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 data bus address 001a 16 transmit buffer register (tb) transmit shift register receive enable signal s rdy1 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial i/o1 output t x d serial i/o1 input r x d write signal to receive/transmit buffer register (address 0018 16 ) overrun error (oe) detection notes 1 : the transmit interrupt (ti) can be selected to occur either when the transmit buffer register has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of t he serial i/o1 control register. 2 : if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the t x d pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ??. d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 35 3874 gr oup single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 29 oper ation of u ar t ser ial i/o function (2) async hr onous serial i/o (u ar t) mode cloc k asynchronous ser ial i/o mode (u ar t) can be selected b y clear ing the ser ial i/o1 mode selection bit (b6) of the ser ial i/o1 control register to 0. eight ser ial data tr ansf er f or mats can be selected, and the tr ansf er f or mats used by a tr ansmitter and receiv er m ust be identical. the tr ansmit and receiv e shift registers each ha v e a b uff er regis- fig. 28 block diagram of uar t serial i/o1 ter , but the two b uff ers ha v e the same address in memor y . since the shift register cannot be written to or read from directl y , transmit data is wr itten to the tr ansmit b uff er , and receiv e data is read from the receiv e b uff er . the tr ansmit b uff er can also hold the ne xt data to be tr ansmitted, and the receiv e b uff er register can hold a char acter while the next char acter is being receiv ed. x in 1/4 oe pe fe 1/16 1/16 data bus receive buffer register address 0018 16 receive shift register receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register data bus transmit shift register address 0018 16 transmit shift register shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 stdetector sp detector uart control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o control register p4 6 /s clk1 serial i/o1 status register p4 4 /r x d p4 5 /t x d tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 ] st d 0 d 1 sp d 0 d 1 st sp transmit buffer write signal ] generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) 1 : error flag detection occurs at the same time that the rbf f lag becomes 1 (at 1st stop bit, during reception). 2 : the transmit interrupt (ti) can be selected to occur when e ither the tbe or tsc flag becomes 1, depending on the sett ing of the transmit interrupt source selection bit (tic) of the serial i/o1 control regist er. 3 : the receive interrupt (ri) is set when the rbf flag becomes 1. 4 : after data is written to the transmit buffer register when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessa ry unti l changing to tsc=0. notes serial i/o output t x d serial i/o input r x d receive buffer read signal transmit or receive clock 36 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [transmit buffer/receive buffer register (tb/rb)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is write-only and the receive buffer register is read-only. if a charac- ter bit length is 7 bits, the msb of data stored in the receive buffer register is 0. [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o1 enable bit (bit 7) of the serial i/o1 control register also clears all the status flags, in- cluding the error flags. all bits of the serial i/o1 status register are initialized to 0 at re- set, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to 1, the transmit shift register shift comple- tion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1. [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register contains eight control bits for the serial i/o1 function. [uart control register (uartcon)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of a data transfer. one bit in this register (bit 4) is always valid and sets the output structure of the p4 5 /t x d pin and p4 6 /s clk1 pin. [baud rate generator (brg)] 001c 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. 37 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 30 structure of serial i/o1 control register brg count source selection bit (css) 0: f(x in ) 1: f(x in )/4 serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o is selected. brg output divided by 16 when uart is selected. 1: external clock input when clockk synchronous serial i/o is selected. external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p4 7 pin operates as ordinary i/o pin 1: p4 7 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: asynchronous serial i/o (uart) 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p4 4 ?4 7 operate as ordinary i/o pins) 1: serial i/o1 enabled (pins p4 4 ?4 7 operate as serial i/o pins) serial i/o1 control register (sio1con : address 001a 16 ) b7 b0 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe) =0 1: (oe) u (pe) u (fe) =1 not used (returns ??when read) serial i/o1 status register (sio1sts : address 0019 16 ) b7 b0 uart control register (uartcon : address 001b 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) not used (return ??when read) b7 b0 38 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o2 the serial i/o2 function can be used only for clock synchronous serial i/o. for clock synchronous serial i/o2, the transmitter and the receiver must use the same clock. when the internal clock is used, transfer is started by a write signal to the serial i/o2 register. [serial i/o2 control register (sio2con)] 001d 16 the serial i/o2 control register contains 8 bits which control vari- ous serial i/o functions. fig. 32 block diagram of serial i/o2 fig. 31 structure of serial i/o2 control register serial i/o2 internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(x in )/8 or f(x cin )/8 0 0 1 : f(x in )/16 or f(x cin )/16 0 1 0 : f(x in )/32 or f(x cin )/32 0 1 1 : f(x in )/64 or f(x cin )/64 1 0 0 : 1 0 1 : 1 1 0 : f(x in )/128 or f(x cin )/128 1 1 1 : f(x in )/256 or f(x cin )/256 s out2 pin selection bit 0 : i/o port 1 : s out2 output pin p7 1 /s out2 ?p7 2 /s clk2 p-channel output disable bit in output mode 0 : cmos 3 state 1 : n-channel open-drain output serial i/o2 transfer direction selection bit 0 : lsb first 1 : msb first s clk2 pin selection bit 0 : external clock (s clk2 function as an i/o port.) 1 : internal clock (s clk2 function as an output port.) s out2 output control bit (when serial data is not transferred) 0 : output active 1 : high-impedance serial i/o2 control register (sio2con : address 001d 16 ) b7 b0 do not set s clk2 pin selection bit external clock p7 2 /s clk2 p7 1 /s out2 p7 0 /s in2 p7 2 latch p7 1 latch serial i/o2 counter (3) serial i/o2 register (8) serial i/o2 interrupt request main clock divide ratio selection bit cm 7 ? ? ? ? ? ? s clk2 divider 1/8 1/16 1/32 1/64 1/128 1/256 serial i/o2 internal synchronous clock selection bits s clk2 pin selection bit s out2 pin selection bit x cin x in ?0 ?0,01,11 data bus 39 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l serial i/o2 operation when writing to the serial i/o2 register (001f 16 ), the serial i/o2 counter is set to 7. after the write is completed, data is output from the s out2 pin each time the transfer clock goes from h to l. in addition, each time the transfer clock goes from l to h, the contents of the se- rial i/o2 register are shifted by 1 bit data is simultaneously received from the s in2 pin. when selecting an internal clock as the transfer clock source, the serial i/o2 counter goes to 0 by counting the transfer clock 8 times, and the transfer clock stops at h, and the interrupt request bit is set to 1. in addition, the s out2 pin becomes the high-im- pedance state after the completion of data transfer. (bit 7 of the serial i/o2 control register does not go to 1 and only the s out2 pin becomes the high-impedance state.) fig. 33 serial i/o2 timing (lsb first) when selecting an external clock as the transfer clock source, the interrupt request bit is set when counting the transfer clock 8 times. however, the transfer clock does not stop, so that control the clock externally. the s out2 pin does not become the high-im- pedance state after completion of data transmit. in order to set the s out2 pin to the high-impedance state when selecting an external clock, set 1 to bit 7 of the serial i/o2 control register after completion of data transmit. also, make sure that s clk2 is at h for this process. when the next data is transmitted (falling of transfer clock), bit 7 of the serial i/o2 control register goes to 0 and the s out2 pin goes to an active state. interrupt request bit set synchronous clock transfer clock serial i/o2 register write signal serial i/o2 output s out2 serial i/o2 input s in2 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 note: when selecting an internal clock after completion of data transmit, the s out2 pin becomes the high-impedance state. (note) 40 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 34 block diagram of serial i/o3 serial i/o3 serial i/o3 has the following modes: 8-bit serial i/o, arbitrary bits from 1 to 256 serial i/o, up to 256-byte auto-transfer serial i/o. the 8-bit serial i/o transfers through serial i/o3 register (address 0013 16 ). the arbitrary bits and auto-transfer serial i/o modes transfer through the 256-byte serial i/o3 auto-transfer ram (ad- dresses 0200 16 to 02ff 16 ). the p8 5 /s rdy3 , p8 6 /s busy3 , and p8 7 /s stb3 pins all have the handshake input/output signal function and can perform active logic high/low selection. p8 5 /s rdy3 p8 6 /s busy3 pin control bits main data bus serial i/o3 automatic transfer controller local data bus serial i/o3 automatic transfer ram (0200 16 to 02ff 16 ) serial i/o3 automatic transfer interval register x cin x in main clock division ratio selection bits serial i/o3 automatic transfer data pointer address decoder main address bus local address bus ?0 ?0,01,11 divider 1/4 1/16 1/32 1/64 1/128 1/256 serial i/o3 interrupt request p8 2 /s out3 p8 3 /s in3 p8 3 latch p8 6 latch serial i/o3 counter serial i/o3 register (8) synchronous circuit serial transfer selection bits serial i/o3 synchronous clock selection bits ?1 ?0,10,11 p8 5 latch p8 4 /s clk3 ? ? ? ? s clk3 external clock serial i/o3 internal synchronous clock selection bits 1/8 1/512 p8 7 latch p8 6 /s busy3 p8 7 /s stb3 (p8 7 /s stb3 pin control bits) p8 5 /s rdy3 p8 6 /s busy3 pin control bits serial transfer status flag ?0,01 ?0,11 ? ? p8 5 /s rdy3 ? ? transfer counter p8 4 latch serial transfer selection bits 41 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 35 structure of serial i/o3 control registers 1 and 2 b7 b0 b7 b0 p8 5 /s rdy3 ? p8 6 /s busy3 pin control bits 0000: p8 5 , p8 6 pins are i/o ports. 0001: unused 0010: p8 5 pin is s rdy3 output, p8 6 pin is i/o port. 0011: p8 5 pin is s rdy3 output, p8 6 pin is i/o port. 0100: p8 5 pin is i/o port, p8 6 pin is s busy3 input. 0101: p8 5 pin is i/o port, p8 6 pin is s busy3 input. 0110: p8 5 pin is i/o port, p8 6 pin is s busy3 output. 0111: p8 5 pin is i/o port, p8 6 pin is s busy3 output. 1000: p8 5 pin is s rdy3 input, p8 6 pin is s busy3 output. 1001: p8 5 pin is s rdy3 input, p8 6 pin is s busy3 output. 1010: p8 5 pin is s rdy3 input, p8 6 pin is s busy3 output. 1011: p8 5 pin is s rdy3 input, p8 6 pin is s busy3 output. 1100: p8 5 pin is s rdy3 output, p8 6 pin is s busy3 input. 1101: p8 5 pin is s rdy3 output, p8 6 pin is s busy3 input. 1110: p8 5 pin is s rdy3 output, p8 6 pin is s busy3 input. 1111: p8 5 pin is s rdy3 output, p8 6 pin is s busy3 input. serial i/o3 control register 2 (sio3con2 (sc32) : address 0015 16 ) p8 2 /s out3 ? p8 4 /s clk3 p-channel output disable bit 0: cmos output (in output mode) 1: n-channel open-drain output (in output mode) s out3 output control bit (when serial data is not transferred) 0: output active 1: output high impedance s busy3 output ? s stb3 output function selection bit (valid in automatic transfer mode) 0: functions as signal for each 1-byte 1: functions as signal for each transfer data set serial transfer status flag 0: serial transfer complete 1: serial transfer in-progress serial i/o3 control register 1 (sio3con1 (sc31) : address 0014 16 ) serial i/o3 synchronous clock selection bits (p8 7 /s stb3 pin control bits) 00 : internal synchronous clock (p8 7 pin is i/o port.) 01 : external synchronous clock (p8 7 pin is i/o port.) 10 : internal synchronous clock (p8 7 pin is s stb3 output.) 11 : internal synchronous clock (p8 7 pin is s stb3 output.) transfer mode selection bit 0 : full duplex (transmit/receive) mode (p8 3 pin is s in3 i/o.) 1 : transmit-only mode (p8 3 pin is i/o port.) serial i/o initialization bit 0 : serial i/o initialization 1 : serial i/o enabled automatic transfer ram transmit/receive address selection bit 0 : transmit/receive address match 200 16 to 2ff 16 (set automatic transfer data pointer to 00 16 to ff 16 .) 1 : transmit address 200 16 to 27f 16 receive address 280 16 to 2ff 16 (set automatic transfer data pointer to 00 16 to 7f 16 .) serial transfer selection bits 00 : serial i/o disabled (p8 2 to p8 7 pins are i/o ports.) 01 : 8-bit serial i/o 10 : arbitrary bit serial i/o 11 : automatic transfer serial i/o (8-bit) serial i/o3 transfer direction selection bit 0 : lsb first 1 : msb first 42 3874 gr oup single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 36 structure of serial i/o3 control register 3 l serial i/o3 operation an internal or external synchronous clock can be selected as the ser ial tr ansf er synchronous cloc k b y the ser ial i/o3 synchronous cloc k selection bits of the ser ial i/o3 control register 1. since the inter nal synchronous cloc k has its o wn b uilt-in divider , 8 types of cloc ks can be selected b y the ser ial i/o3 internal synchro- nous clock selection bits of the serial i/o3 control registe r 3. either i/o por t or handshak e i/o signal function can be selected f or the p8 5 /s rd y3 , p8 6 /s b usy3 , and p8 7 /s stb3 pins b y the ser ial i/o3 synchronous clock selection bits (p8 7 /s stb3 pin control bits) of the serial i/o3 control register 1 or the p8 5 /s rdy3 p8 6 /s busy3 pin control bits of the serial i/o3 control register 2. cmos output or n-channel open-dr ain output can be selected for the s clk3 and s out3 output pins b y the p8 2 /s out3 p8 4 /s clk3 p- channel output disab le bit of the ser ial i/o3 control register 2. the s out3 output control bit of the serial i/o3 control register 2 can be used to select the status of the s out3 pin when serial data is not transferred; either output active or high-impedance. how- e v er , when selecting an exter nal synchronous cloc k, the s out3 pin can go to the high-impedance status by setting the s out3 out- put control bit to 1 when s clk3 input is at h after transfer completion. when the next serial transfer begins and s clk3 goes to l, the s out3 output control bit is automatically reset to 0 and goes to an output active status. regardless of selecting an internal or external synchronous clock, the serial transfer has both a full duplex mode as well as a trans- mit-only mode . these modes are set by the tr ansf er mode selection bit of serial i/o3 control register 1. lsb first or msb first can be selected f or the input/output order of the ser ial tr ansf er bit str ing b y the serial i/o3 tr ansfer direction se- lection bit of ser ial i/o3 control register 1. in order to use serial i/o3, the follo wing process must be f ollo w ed after all of the above set have been completed: first, selec t any one of 8-bit serial i/o, arbitrary bit serial i/o, or auto-t ransfer serial i/o by setting the serial transfer selection bits of the ser ial i/o3 control register 1. then, enab le the serial i/o by setting the ser ial i/o initialization bit of the serial i/o3 control register 1 to 1. whether using an inter nal or e xter nal synchronous cloc k, set the ser ial i/o initialization bit to 0 when ter minating a ser ial tr ansf er dur ing the tr ansmission. b7 b0 serial i/o3 control register 3 (sio3con3 (sc33) : address 0016 16 ) serial i/o3 internal synchronous clock selection bits 000: f(x in )/4 or f(x cin )/4 001: f(x in )/8 or f(x cin )/8 010: f(x in )/16 or f(x cin )/16 011: f(x in )/32 or f(x cin )/32 100: f(x in )/64 or f(x cin )/64 101: f(x in )/128 or f(x cin )/128 110: f(x in )/256 or f(x cin )/256 111: f(x in )/512 or f(x cin )/512 auto-transfer interval set bit 00000: 2 cycles of transfer clock 00001: 3 cycles of transfer clock : 11110: 32 cycles of transfer clock 11111: 33 cycles of transfer clock written to latch read from decrement counter 43 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 37 structure of serial i/o3 automatic transfer data pointer (1) 8-bit serial i/o mode address 0013 16 is the serial i/o3 register. when selecting an inter- nal synchronous clock, serial transfer of the 8-bit serial i/o starts by the write signal to the serial i/o3 register (address 0013 16 ). the serial transfer status flag of the serial i/o3 control register 2 indicates the serial i/o3 register status. the flag is set to 1 by a serial i/o3 register write, which triggers a transfer start. after the 8-bit transfer is completed, the flag is reset to 0 and a serial i/o3 interrupt request occurs simultaneously. when an external synchronous clock is selected, the contents of the serial i/o3 register are continually shifted while the transfer clock inputs to s clk3 . in this case, control the clock externally. (2) auto-transfer serial i/o mode since read and write to the serial i/o3 register are controlled by the serial i/o3 automatic transfer controller, address 0013 16 func- tions as the transfer counter (in byte units). in order to make a serial transfer through the serial i/o3 automatic transfer ram (addresses 0200 16 to 02ff 16 ), it is necessary to set the serial i/o3 automatic transfer data pointer before transferring data. the automatic transfer data pointer set bits indicate the low- order 8 bits of the start data stored address. the automatic transfer ram transmit/receive address select bit can divide the 256-byte serial i/o3 automatic transfer ram into two areas: 128- byte transmit data area and 128-byte receive data area. when an internal synchronous clock is selected and any of the fol- lowing conditions apply, the transfer interval between each 1-byte data can be set by the automatic transfer interval set bits of the serial i/o3 control register 3: 1. the handshake signal is not used. 2. the handshake signals s rdy3 output, s busy3 output, and s stb3 output are used independently. 3. the handshake signals output is used in groups: s rdy3 /s stb3 output or s busy3 /s stb3 . there are 32 values among 2 and 33 cycles of the transfer clock. when the automatic transfer interval setting is valid and s busy3 output is used, and the s busy3 and s stb3 output function as sig- nal for each transfer data set by the s busy3 output?s stb3 output function selection bit, there is the transfer interval before the first data is transmitted/received, as well as after the last data is trans- mitted/received. when using s stb3 output, regardless of the contents of the s busy3 output ? s stb3 output function selection bit, this transfer interval become 2 cycles longer than the value set for each 1-byte data. in addition, when using the combined output of s busy3 and s stb3 as the signal for each transfer data set, the transfer interval after completion of transmission/receipt of the last data become 2 cycles longer than the set value. when selecting an external synchronous clock, the automatic transfer interval cannot be set. after all of the above bit settings have been completed, and an in- ternal synchronous clock has been selected, serial automatic transfer starts when the value of the number of transfer bytes, decremented by 1, is written to the transfer counter (address 0013 16 ). when an external synchronous clock is selected, write the value of the transfer bytes, decremented by 1, to the transfer counter, and input the transfer clock to s clk3 after 5 or more cycles of internal clock f . set the transfer interval of each 1-byte data transmission to 5 or more cycles of the internal clock f after the rising edge of the last bit of a 1-byte data. regardless of internal or external synchronous clock, the auto- matic transfer data pointer and transfer counter are both decremented after receipt of each 1-byte data is completed and it is written to the automatic transfer ram. the serial transfer status flag is set to 1 by writing to the transfer counter which triggers the start of transmission. after the last data is written to the auto- matic transfer ram, the serial transfer status flag is set to 0 and a serial i/o3 interrupt request occurs simultaneously. the write values of the automatic transfer data pointer set bits and the automatic transfer interval set bits are kept in the latch. as a transfer counter write occurs, each value is transferred to its corre- sponding decrement counter. b7 b0 serial i/o3 automatic transfer data pointer (sio3dp : address 0017 16 ) automatic transfer data pointer set bits indicates the low-order 8 bits of the address stored the start data on the serial i/o3 automatic transfer ram. write: kept in latch read: from decrement counter 44 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers (3) arbitrary bit serial i/o mode since read and write of the serial i/o3 register are controlled by the serial i/o3 automatic transfer controller, address 0013 16 func- tions as the transfer counter (in byte units). after the serial i/o3 automatic transfer data pointer and automatic transfer interval set bits have been set, and an internal synchro- nous clock selected, serial automatic transfer starts when the value of the number of transfer bits decremented by 1 is written to the transfer counter (address 0013 16 ), just as in the automatic transfer serial i/o. when selecting an external synchronous clock, write the value of the transfer bits decremented by 1 to the trans- fer counter, then input the transfer clock to s clk3 after 5 or more cycles of internal clock f . the transfer interval after each 8-bit data transfer must be 5 or more cycles of internal clock f after the ris- ing edge of the last bit of the 8-bit data. when selecting an internal synchronous clock, the automatic transfer interval can be specified regardless of the contents of the selected handshake signal. in this case, when the automatic transfer interval setting is valid and s busy3 output is used there are the transfer interval before the first data is transmitted/received, as well as after the last data is transmitted/received just as in the automatic transfer serial i/o mode. when using s stb3 output, this transfer interval become 2 cycles longer than the value set for each 8-bit data. in addition, when using the combined output of s busy3 and s stb3 , the trans- fer interval after completion of transmission/receipt of the last data become 2 cycles longer than the set value. fig. 38 automatic transfer serial i/o operation when selecting an external synchronous clock, the automatic transfer interval cannot be specified. regardless of internal or external synchronous clock, the auto- matic transfer data pointer is decremented after each 8-bit data is received and then written to the auto-transfer ram. the transfer counter is decremented with the transfer clock. the serial transfer status flag is set to 1 by writing to the transfer counter which trig- gers the start of transmission. after the last data is written to the automatic transfer ram, the serial transfer status flag is set to 0 and a serial i/o3 interrupt request occurs simultaneously. the write values of the automatic transfer data pointer set bits and the automatic transfer interval set bits are kept in the latch. as a transfer counter write occurs, each value is transferred to its corre- sponding decrement counter. if the last data does not fill 8 bits, the receive data stored in the se- rial i/o3 automatic transfer ram become the closest msb odd bit if the transfer direction select bit is set to lsb first, or the closest lsb odd bit if the transfer direction select bit is set to msb first. 2ff 16 automatic transfer ram transfer counter automatic transfer data pointer serial i/o3 register 252 16 251 16 250 16 24f 16 24e 16 200 16 04 16 52 16 s in3 s out3 45 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 39 arbitrary bit serial i/o operation 9 214 16 214 16 215 16 start bit automatic transfer ram (after transfer) 0010110 215 16 1 101001 msb lsb receive bit string odd bit s in3 lsb first automatic transfer ram (before transfer) 00110101 transfer counter 101011 msb lsb automatic transfer data pointer 15 16 0d 16 s out3 s in3 s clk3 (internal synchronous clock selected) serial transfer status flag transfer counter write transfer counter automatic transfer data pointer automatic transfer ram serial i/o3 register serial i/o3 register automatic transfer ram *according to automatic transfer interval setting d 16 c 16 b 16 a 16 6 7 8 5 43210 15 16 14 16 transmit bit string odd bit s out3 lsb first start bit * when using the s stb3 output signal, this become 2 transfer clock cycles longer than the set interval. 1 0 1 011 00110101 1 0 1 001 10010110 46 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l s busy3 input signal the s busy3 input is a signal which receives a request for a stop of transmission/reception from the serial transfer destination. when the internal synchronous clock is selected, input an h level signal into the s busy3 input and an l level signal into the s busy3 input in the initial status in which transfer is stopped. when starting a transmit/receive operation, input an l level signal into the s busy3 input and an h level signal into the s busy3 input in the period of 1.5 cycles or more of the transfer clock. then, transfer clocks are output from the s clk3 output. when an h level signal is input into the s busy3 input and an l level signal into the s busy3 input after a transmit/receive operation is started, this transmit/receive operation are not stopped immedi- ately and the transfer clocks from the s clk3 output are not stopped until the specified number of bits is transmitted and re- ceived. the handshake unit of the 8-bit serial i/o is 8 bits and that of the arbitrary bit serial i/o is the bit number adding 1 to the set value to the transfer counter, and that of the automatic transfer serial i/o is 8 bits. handshake signal l s stb3 output signal the s stb3 output is a signal to inform an end of transmission/re- ception to the serial transfer destination . the s stb3 output signal can be used only when the internal synchronous clock is selected. in the initial status, that is, in the status in which the serial i/o ini- tialization bit (b4) is reset to 0, the s stb3 output goes to l, and the s stb3 output goes to h. at the end of transmit/receive operation, when the data of the se- rial i/o3 register is all output from s out3 , pulses which are the s stb3 output of h and the s stb3 output of l are output in the period of 1 cycle of the transfer clock. after that, each pulse is re- turned to the initial status in which s stb3 output goes to l and the s stb3 output goes to h. furthermore, after 1 cycle, the serial transfer status flag (b5) is re- set to 0. in the automatic transfer serial i/o mode, whether making the s stb3 output active at an end of each 1-byte data or after comple- tion of transfer of all data can be selected by the s busy3 output ? s stb3 output function selection bit (b4 of address 0015 16 ) of serial i/o3 control register 2. when the external synchronous clock is selected, input an h level signal into the s busy3 input and an l level signal into the s busy3 input in the initial status in which transfer is stopped. at this time, the transfer clocks to be input in s clk3 become invalid. during serial transfer, the transfer clocks to be input in s clk3 be- come valid, enabling a transmit/receive operation, while an l level signal is input into the s busy3 input and an h level signal is input into the s busy3 input. when changing the input values in to the s busy3 input and the s busy3 input in these operations, change them while the s clk3 in- put is in a high state. when the high impedance of the s out3 output is selected by the s out3 output control bit (b6), the s out3 output becomes active, enabling serial transfer by inputting a transfer clock to s clk3 , while an l level signal is input into the s busy3 input and an h level signal is input into the s busy3 input. fig. 40 s stb3 output operation fig. 41 s busy3 input operation (internal synchronous clock) l s busy3 output signal the s busy3 output is a signal which requests a stop of transmis- sion/reception to the serial transfer destination. in the automatic transfer serial i/o mode, regardless of the internal or external syn- chronous clock, whether making the s busy3 output active at transfer of each 1-byte data or during transfer of all data can be selected by the s busy3 output ? s stb3 output function selection bit (b4). in the initial status, that is, the status in which the serial i/o initial- ization bit (b4) is reset to 0, the s busy3 output goes to h and the s busy3 output goes to l. fig. 42 s busy3 input operation (external synchronous clock) s stb3 s clk3 s out3 s busy3 s clk3 s out3 s busy3 s clk3 s out3 invalid (output high-impedance) 47 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers when the internal synchronous clock is selected, in the 8-bit serial i/o mode and the automatic transfer serial i/o mode (s busy3 out- put function outputs in 1-byte units), the s busy3 output goes to l and the s busy3 output goes to h before 0.5 cycle (transfer clock) of the timing at which the transfer clock from the s clk3 output goes to l at a start of transmit/receive operation. in the automatic transfer serial i/o mode (the s busy3 output func- tion outputs all transfer data), the s busy3 output goes to l and the s busy3 output goes to h when the first transmit data is writ- ten into the serial i/o3 register (address 0013 16 ). when the external synchronous clock is selected, the s busy3 out- put goes to l and the s busy3 output goes to h when transmit data is written into the serial i/o3 register to start a transmit operation, regardless of the serial i/o transfer mode. at termination of transmit/receive operation, the s busy3 output returns to h and the s busy3 output returns to l, the initial status, when the serial transfer status flag is set to 0, regardless of selecting the internal or external synchronous clock. furthermore, in the automatic transfer serial i/o mode (s busy3 output function outputs in 1-byte units), the s busy3 output goes to h and the s busy3 output goes to l each time 1-byte of receive data is written into the automatic transfer ram. fig. 43 s busy3 output operation (internal synchronous clock, 8-bits serial i/o) fig. 44 s busy3 output operation (external synchronous clock, 8-bits serial i/o) fig. 45 s busy3 output operation in automatic transfer serial i/o mode (internal synchronous clock, s busy3 output function outputs each 1-byte) s busy3 s clk3 s out3 serial transfer status flag serial transfer status flag s busy3 s clk3 write to serial i/o3 register s clk3 s busy3 s out3 automatic transfer interval serial transfer status flag automatic transfer ram serial i/o3 register serial i/o3 register automatic transfer ram 48 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers l s rdy3 output signal the s rdy3 output is a transmit/receive enable signal which in- forms the serial transfer destination that transmit/receive is ready. in the initial status, that is, when the serial i/o initialization bit (b4) is reset to 0, the s rdy3 output goes to l and the s rdy3 output goes to h. after transmitted data is stored in the serial i/o3 reg- ister (address 0013 16 ) and a transmit/receive operation becomes ready, the s rdy3 output goes to h and the s rdy3 output goes to l. when a transmit/receive operation is started and the transfer clock goes to l, the s rdy3 output goes to l and the s rdy3 out- put goes to h. l s rdy3 input signal the s rdy3 input signal becomes valid only when the s rdy3 input and the s busy3 output are used. the s rdy3 input is a signal for re- ceiving a transmit/receive ready completion signal from the serial transfer destination. when the internal synchronous clock is selected, input a low level signal into the s rdy3 input and a high level signal into the s rdy3 input in the initial status in which the transfer is stopped. when an h level signal is input into the s rdy3 input and an l level signal is input into the s rdy3 input for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the s clk3 output and a transmit/receive operation is started. after the transmit/receive operation is started and an l level sig- nal is input into the s rdy3 input and an h level signal into the s rdy3 input, this operation cannot be immediately stopped. after the specified number of bits are transmitted and received, the transfer clocks from the s clk3 output is stopped. the hand- shake unit of the 8-bit serial i/o and that of the automatic transfer serial i/o are of 8 bits. that of the arbitrary bit serial i/o is the bit number adding 1 to the set value to the transfer counter. when the external synchronous clock is selected, the s rdy3 input becomes one of the triggers to output the s busy3 signal. to start a transmit/receive operation (s busy3 output to l, s busy3 output to h), input an h level signal into the s rdy3 input and an l level signal into the s rdy3 input, and also write transmit data into the serial i/o3 register. fig. 46 s busy3 output operation in arbitrary bit serial i/o mode (internal synchronous clock) fig. 47 s rdy3 output operation fig. 48 s rdy3 input operation (internal synchronous clock) s clk3 s busy3 s out3 serial transfer status flag automatic transfer ram serial i/o3 register serial i/o3 register automatic transfer ram automatic transfer interval transfer interval transfer interval s rdy3 s clk3 write to serial i/o3 register s rdy3 s clk3 s out3 49 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 49 handshake operation at serial i/o3 mutual connecting (1) a: b: s clk3 s rdy3 s busy3 s busy3 s rdy3 s clk3 a: b: write to serial i/o3 register s clk3 s rdy3 s busy3 internal synchronous clock selection external synchronous clock selection write to serial i/o3 register a: b: s clk3 s rdy3 s busy3 s busy3 s rdy3 s clk3 a: b: write to serial i/o3 register s clk3 s rdy3 s busy3 internal synchronous clock selection external synchronous clock selection write to serial i/o3 register fig. 50 handshake operation at serial i/o3 mutual connecting (2) 50 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers data link layer communication control circuit the 3874 group has a built-in data link layer communication con- trol circuit. this data link layer communication control circuit is applicable for multi-master serial bus communication control used only with data lines through an external driver/receiver. the data link layer communication control circuit consists of fol- lowing. ?communication mode register (address 002a 16 ) ?transmit control register (address 002b 16 ) ?transmit status register (address 002c 16 ) ?receive control register (address 002d 16 ) ?receive status register (address 002e 16 ) ?bus interrupt factor determination control register (address 002f 16 ) ?control field select register (address 0030 16 ) ?control field data register (address 0031 16 ) ?transmit/receive fifo (address 0032 16 ) this function is realized by hardware and firmware so that com- munication protocol can be partially modified according to the users specification. the following are the standard communication rate and functions which the data link layer communication control circuit can per- form. ?communication rate: approx. 40 kbps the communication rate depends on frame or bit protocol. ?synchronous method: half-duplex asynchronous ?modification method: pwm method, nrz, etc. ?communication functions: bus arbitration (csma/cd method, etc.) error detection (parity, acknowledge, crc, etc.) a frame, data retry the transmission signal is output from the bus out pin and input to the bus in pin. detailed specifications for communication protocol, bit assign- ment, function, etc. of each register are defined according to each communication protocol specification confirmation. 51 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 51 data link layer communication control circuit block example data bus local address * each register name is defined according to the communication protocol specifications. bus in /bus out input/output control circuit bus in bus out bus interrupt request signal local data bus bus interrupt source control signal to interrupt request register bus interrupt source determination control register (address 002f 16 ) control field selection register (address 0030 16 ) control field register (address 0031 16 ) communication mode register (address 002a 16 ) transmit control register (address 002b 16 ) transmit status register (address 002c 16 ) receive control register (address 002d 16 ) receive status register (address 002e 16 ) transmit/receive fifo (address 0032 16 ) transmit fifo (8 bytes) receive fifo (16 bytes) * register crowd 14 bytes local address (addresses 00 16 to 0d 16 ) 52 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers b7 b0 communication mode register (busm : address 002a 16 ) arbitrary bits: defined according to each communication protocol specification confirmation. not used (always write 00 to these bits.) [communication mode register (busm)] 002a 16 the communication mode register (address 002a 16 ) has 6 bits and consists of all the control bits for the communication mode. fig. 52 structure of communication mode register 53 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [transmit control register (txdcon)] 002b 16 the transmit control register (address 002b 16 ) has 7 bits and con- sists of the transmit control and transmit status flags. [transmit status register (txdsts)] 002c 16 the transmit status register (address 002c 16 ) has 8 bits and con- sists of the transmit error flag and transmit interrupt request flag. fig. 53 structure of transmit control register fig. 54 structure of transmit status register transmit control register (txdcon : address 002b 16 ) arbitrary bits: defined according to each communication protocol specification confirmation. not used (return 0 when read) arbitrary bits: defined according to each communication protocol specification confirmation. b7 b0 transmit status register (txdsts : address 002c 16 ) arbitrary bits: defined according to each communication protocol specification confirmation. transmit bus interrupt source 1 request bit transmit bus interrupt source 2 request bit arbitrary bits: defined according to each communication protocol specification confirmation. transmit bus interrupt source 3 request bit b7 b0 when a transmit bus interrupt source request bit is 1, an interrupt request occurs. the name and function of each transmit bus interrupt source is defined according to the communication protocol specification confirmation. note: bits 0 to 3, bit 5, and bit 7 can be cleared only by software. 54 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [receive control register (rxdcon)] 002d 16 the receive control register has 7 bits and consists of the receive control and receive status flags. [receive status register (rxdsts)] 002e 16 the receive status register has 8 bits and consists of the receive error flag and receive interrupt request flags. fig. 55 structure of receive control register fig. 56 structure of receive status register receive control register (rxdcon : address 002d 16 ) arbitrary bits: defined according to each communication protocol specification confirmation. not used (return 0 when read) arbitrary bits: defined according to each communication protocol specification confirmation. b7 b0 receive status register (rxdsts : address 002e 16 ) arbitrary bits: defined according to each communication protocol specification confirmation. receive bus interrupt source 1 request bit receive bus interrupt source 2 request bit arbitrary bits: defined according to each communication protocol specification confirmation. receive bus interrupt source 3 request bit b7 b0 when a receive bus interrupt source request bit is 1, an interrupt request occurs. the name and function of each receive bus interrupt source is defined according to the communication protocol specification confirmation. 55 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [control field selection register (cfsel)] 0030 16 [control field register (cf)] 0031 16 the control field data select the control field selection register (ad- dress 0030 16 ) value as the pointer. the data can be confirmed and changed by a read/write of the control field register (address 0030 16 ). for example, when reading/writing the local address 00 16 , the control field selection register is set to 00 16 and the control field register is read/written. fig. 57 structure of control field selection register control field selection register (cfsel : address 0030 16 ) control field selection bits b3 b2 b1 b0 0 0 0 0 : 0 0 0 1 : 0 0 1 0 : 0 0 1 1 : 0 1 0 0 : 0 1 0 1 : 0 1 1 0 : 0 1 1 1 : 1 0 0 0 : 1 0 0 1 : 1 0 1 0 : 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : disabled 1 1 1 1 : disabled not used (write 0 to these bits.) b7 b0 arbitrary bits: defined according to each communication protocol specification confirmation. 56 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers [bus interrupt source determination control register (bicond)] 002f 16 the bus interrupt source determination control register (address 002f 16 ) has 6 bits and controls bus-related interrupts. refer to fig. 58 structure of bus interrupt source determination control register the section concerning interrupts for details about priority and vec- tor addresses. bus interrupt source determination control register (bicond : address 002f 16 ) transmit bus interrupt source 1 enable bit transmit bus interrupt source 2 enable bit not used (return 0 when read) transmit bus interrupt source 3 enable bit receive bus interrupt source 1 enable bit receive bus interrupt source 2 enable bit receive bus interrupt source 3 enable bit not used (return 0 when read) 0: interrupt disabled 1: interrupt enabled the name and function of each transmit/receive bus interrupt source is defined according to the communication protocol specification confirmation. b7 b0 57 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers a-d converter [a-d/d-a conversion register (ad)] 0035 16 the a-d/d-a conversion register is a register (at reading) that con- tains the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. [a-d control register (adcon)] 0034 16 the a-d control register controls the a-d/d-a conversion process. bits 0 to 2 of this register select specific analog input pins. bit 3 signals the completion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion, then changes to 1 when the a-d conversion is completed. writing 0 to this bit starts the a-d conversion. when bit 5, which is the ad external trigger valid bit, is set to 1, this bit enables a-d conversion even by a falling edge of an adt input. set 0 (input port) to the direction register corresponding the adt pin. bit 6 is the interrupt source selection bit. writing 0 to this bit, a-d converter interrupt request occurs at completion of a-d conversion. writing 1 to this bit the interrupt request occurs at falling edge of an adt input. comparison voltage generator the comparison voltage generator divides the voltage between av ss and v ref by 256, and outputs the divided voltages. channel selector the channel selector selects one of the input ports p6 7 /an 7 to p6 0 /an 0 and inputs it to the comparator. comparator and control circuit the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the a-d/ d-a conversion register. when an a-d conversion is completed, the control circuit sets the ad conversion completion bit and the ad conversion interrupt request bit to 1. fig. 60 block diagram of a-d converter note that the comparator is constructed linked to a capacitor, so set f(x in ) to at least 500 khz during a-d conversion. use a cpu system clock dividing the main clock x in . fig. 59 structure of a-d control register a-d control register (adcon : address 0034 16 ) analog input pin selection bits 000: p6 0 /an 0 001: p6 1 /an 1 010: p6 2 /an 2 011: p6 3 /an 3 100: p6 4 /an 4 101: p6 5 /an 5 110: p6 6 /an 6 111: p6 7 /an 7 ad conversion completion bit 0: conversion in progress 1: conversion completed v ref input switch bit 0: off 1: on ad external trigger valid bit 0: ad external trigger invalid 1: ad external trigger valid interrupt source selection bit 0: interrupt request at a-d conversion completed 1: interrupt request at adt input falling da output enable bit 0: da output disabled 1: da output enabled b7 b0 channel selector a-d control circuit a-d conversion register resistor ladder av ss v ref comparator adt/a-d interrupt request b7 b0 a-d control register 3 p6 0 /an 0 p6 1 /an 1 p6 2 /an 2 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p6 7 /an 7 8 p7 7 /adt data bus 58 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers d-a converter the 3874 group has an on-chip d-a converter with 8-bit resolution and 1 channel. the d-a conversion is performed by setting the value in the a-d/d-a conversion register. the result of d-a con- verter is output from da pin by setting the da output enable bits to 1. when using the d-a converter, the corresponding port direc- tion register bit (p8 0 /da) should be set to 0 (input status). the output analog voltage v is determined by the value n (base 10) in the a-d/d-a conversion register as follows: v=v ref 5 n/256 (n=0 to 255) where v ref is the reference voltage. at reset, the d-a conversion registers are cleared to 00 16 , the da output enable bits are cleared to 0, and p8 0 /da pin becomes high impedance. the da output is not buffered, so connect an ex- ternal buffer when driving a low-impedance load. when using d-a converter, set 4.0 v or more to v cc . n note when reading the a-d/d-a conversion register, the a-d conver- sion result is read, and the set value for d-a conversion is not read. fig. 61 block diagram of d-a converter fig. 62 equivalent connection circuit of d-a converter p8 0 /da data bus d-a conversion register (8) r-2r resistor ladder da output enable bit av ss v ref 0 1 msb 0 1 r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r lsb 2r p8 0 /da d-a conversion register da output enable bit 59 3874 gr oup single-chip 8-bit cmos microcomputer mitsubishi microcomputers w a tchdog timer the watchdog timer giv es a mean of retur ning to the reset status when a prog r am cannot r un on a nor mal loop (f or e xample, be- cause of a softw are r un-a w a y). the w atchdog timer consists of an 8-bit w atchdog timer l and a 12-bit w atchdog timer h. w atchdog timer initial v alue w atchdog timer l is set to ff 16 and w atchdog timer h is set to fff 16 by writing to the watchdog timer control register or at a re- set. an y wr ite instr uction that causes a wr ite signal can be used, such as the st a, ldm, clb , etc. data can only be wr itten to bits 6 and 7 of the w atchdog control register . regardless of the v alue written to bits 0 to 5, the above-mentioned value will be se t to each timer . w atchdog timer operations the watchdog timer stops at reset and a countdo wn is star ted by the wr iting to the watchdog timer control register . an inter nal reset occurs when w atchdog timer h underflo ws . the reset is released after its release time. after the release , the progr am is restar ted from the reset v ector address . usually , wr ite to the watchdog timer control register by software before an underflow of the watc hdog timer h. the w atchdog timer does not function if the w atchdog timer control register is not written to at least once. when bit 6 of the watchdog timer control register is kept at 0, the stp instruction is enabled. when that is executed, both the clock and the watchdog timer stop. count re-starts at the same tim e as the release of stop mode (note) . the w atchdog timer does not stop while a wit instruction is executed. in addition, the s tp in- struction is disabled by writing 1 to this bit again. when the stp instruction is executed at this time, it is processed as an undefined instruction, and an internal reset occurs. once a 1 is wr itten to this bit, it cannot be programmed to 0 again. the following shows the period between the write execution t o the watchdog timer control register and the underflow of watchdo g timer h. bit 7 of the w atchdog timer control register is 0: when x cin = 32 khz; 524 s when x in = 6.4 mhz; 2.6 s bit 7 of the w atchdog timer control register is 1: when x cin = 32 khz; 2 s when x in = 6.4 mhz; 10 ms note: the watchdog timer continues to count even while waiting for a stop release. therefore, make sure that watchdog timer h does not un- derflow during this period. fig. 63 bloc k diag r am of w atchdog timer fig. 64 str ucture of w atchdog timer control register x in data bus x cin 10 00 01 11 main clock division ratio selection bits (note) 0 1 1/16 watchdog timer h count source selection bit reset circuit stp instruction disable bit watchdog timer h (12) ff 16 is set when watchdog timer control register is written to. internal reset reset watchdog timer l (8) note: either double-speed, high-speed, middle-speed, or low-speed mode is selected by bits 7 and 6 of the cpu mode register. stp instruction ff 16 is set when watchdog timer control register is written to. reset release time wait b0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer h (for read-out of high-order 6 bit) watchdog timer control register (wdtcon : address 001e 16 ) b7 60 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers reset circuit to reset the microcomputer, reset pin should be held at an l level for 2 m s or more. then the reset pin is returned to an h level (the power source voltage should be between 3.0 v and 5.5 v, and the oscillation should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low- order byte). make sure that the reset input voltage is 0.6 v or less for v cc of 3.0 v. fig. 66 reset sequence fig. 65 reset circuit example (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc=2.5 v fffc fffd ad h ,ad l ad l ad h reset internal reset address data sync f ???? x in x in : 40 to 56 clock cycles reset address from the vector table 1: the frequency relation of f(x in ) and f( f ) is f(x in )=8 ?f( f ). 2: the question marks (?) indicate an undefined state that depends on the previous state. notes 61 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 67 internal status at reset (1) port p0 (2) port p0 direction register (3) port p1 (4) port p1 direction register (5) port p2 (6) port p2 direction register (7) port p3 (8) port p3 direction register (9) port p4 (10) port p4 direction register (11) port p5 (12) port p5 direction register (13) port p6 (14) port p6 direction register (15) port p7 (16) port p7 direction register (17) port p8 (18) port p8 direction register (19) port p9 (20) serial i/o3 control register 1 (21) serial i/o3 control register 2 (22) serial i/o3 control register 3 (23) serial i/o3 automatic transfer data pointer (24) serial i/o1 status register (25) serial i/o1 control register (26) uart control register (27) serial i/o2 control register (28) watchdog timer control register (29) timer x (low-order) (30) timer x (high-order) ff 16 ff 16 ff 16 ff 16 00 16 00 16 00 16 20 16 00 16 10 16 01 16 00 16 00 16 00 16 08 16 00 16 00 16 00 16 00 16 00 16 48 16 00 16 00 16 00 16 00 16 fffd 16 contents fffc 16 contents register contents address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0014 16 0015 16 0016 16 0017 16 0019 16 001a 16 001b 16 001d 16 001e 16 0020 16 0021 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 80 16 00 16 e0 16 00 16 3f 16 ff 16 ff 16 register contents address notes: 5 : not fixed notes: since the initial values for other than above-mentioned registers and ram contents are indefinite at reset, they must be set. (31) timer y (low-order) (32) timer y (high-order) (33) timer 1 (34) timer 2 (35) timer 3 (36) timer x mode register (37) timer y mode register (38) timer 123 mode register (39) communication mode register (40) transmit control register (41) transmit status register (42) receive control register (43) receive status register (45) control field selection register (46) pull up register (47) a-d control register (48) interrupt source discrimination register 2 (50) interrupt source discrimination register 1 (52) interrupt edge selection register (53) cpu mode register (54) interrupt request register 1 (55) interrupt request register 2 (56) interrupt control register 1 (57) interrupt control register 2 (58) processor status register (59) program counter 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0033 16 0034 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 (ps) (pch) (pcl) 0022 16 0023 16 0024 16 0025 16 0026 16 5 000000 000 555 0 0 0 55 1 5 555 5 (44) bus interrupt source discrimination control register (49) interrupt source discrimination control register 2 (51) interrupt source discrimination control register 1 01 16 62 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers clock generating circuit the 3874 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturers recommended values. no exter- nal resistor is needed between x in and x out since a feed-back resistor exists on-chip. however, an external feed-back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. when using the x cin oscillation circuit, x cin and x cout pins pull- up resistors need to be invarid. frequency control (1) middle-speed mode the internal clock f is the frequency of x in divided by 8. after re- set, this mode is selected. (2) double-speed mode the internal clock f is the frequency of x in . (3) high-speed mode the internal clock f is half the frequency of x in . (4) low-speed mode the internal clock f is half the frequency of x cin . n note when switching the mode between double/middle/high-speed and low-speed, stabilize both x in and x cin oscillations. sufficient time is required for the sub clock to stabilize, especially immediately af- ter power on and at returning from stop mode. when switching the mode between double/middle/high-speed and low-speed, set the frequency on condition that f(x in ) > 3f(x cin ). it takes the cycle number mentioned below to switch between each mode (machine cycle = cycle of internal clock f ). double-speed mode ? except double-speed mode 1 to 8 machine cycles high-speed mode ? except high-speed mode 1 to 4 machine cycles middle-speed mode ? except middle-speed mode 1 machine cycle low-speed mode ? except low-speed mode 1 to 4 machine cycles the 3874 group operates in the previous mode while the mode is switched. (5) low power dissipation mode the low power consumption operation can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to 1. when the main clock x in is restarted (by setting the main clock stop bit to 0), set sufficient time for oscillation to stabilize. by clearing furthermore the x cout drivability selection bit (b3) of the cpu mode register to 0, low power consumption operation can be realized by reducing the drivability between x cin and x cout . at reset or during stp instruction execution this bit is set to 1 and a reduced drivability that has an easy oscillation start is set. the sub-clock x cin -x cout oscillating circuit can no directly in- put clocks that are generated externally. accordingly, make sure to cause an external resonator to oscillate. oscillation control (1) stop mode when the stp instruction is executed, the internal clock f stops at an h level, and x in and x cin oscillators stop. the value set to the timer 1 latch and the timer 2 latch is set to timer 1 and timer 2. ei- ther x in or x cin divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. the bits of the timer 123 mode register except the timer 3 count source selection bit (b4) are cleared to 0. set the interrupt enable bits of timer 1 and timer 2 to the disabled state (0) before executing the stp in- struction. oscillator restarts at reset or when an external interrupt is re- ceived, but the internal clock f is not supplied to the cpu until timer 2 underflows. this allows time for the clock circuit oscillation to stabilize. timer 1 latch and timer 2 latch should be set to proper values for stabilizing oscillation before executing the stp instruc- tion. (2) wait mode if the wit instruction is executed, the internal clock f stops at an h level. the states of x in and x cin are the same as the state be- fore executing the wit instruction. the internal clock f restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. fig. 68 ceramic resonator circuit fig. 69 external clock input circuit x cin x cout x in x out c in c out c cin c cout rf rd x cin x cout x in x out open external oscillation circuit v cc v ss c cin c cout rf rd 63 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timing f (internal clock) timer 2 count source selection bit wit instruction stp instruction s r q stp instruction s r q main clock stop bit s r q timer 2 timer 1 1/2 1/4 x in x out x cout x cin interrupt request interrupt disable flag i reset 1/16 1/2 port x c switch bit ? ? ? ? timer 1 count source selection bit ? ? ?0 ?0,01,11 ?1 ?0,10 note: when low-speed mode is selected, set port x c switch bit (b4) to ?. main clock division ratio selection bits (note) main clock division ratio selection bits (note) ?1 fig. 70 system clock generating circuit block diagram 64 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 71 state transitions of system clock 0 ? 1 reset notes 1: switch the mode by the arrows shown between the mode blocks. (do not switch between the modes directly without an arrow.) 2: all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: timer operates in the wait mode. 4: when the stop mode is ended, wait time is generated automatically by connecting timer 1 and timer 2. 5: the example assumes that 6.3 mhz is being applied to the x in pin and 32 khz to the x cin pin. f indicates the internal clock. 6: we recommend that x cout drivability selection bit is set to 1 (high) because reliance of oscillation stability is improved. high-speed mode ( f =3.15 mhz) cm 7 =0 high-speed mode cm 6 =0 6.3 mhz selected cm 5 =0 (x in oscillating) cm 4 =0 (32 khz stopped) cm 3 =1 (x cout drivability high) middle-speed mode ( f =788 khz) cm 7 =0 middle-speed mode cm 6 =1 6.3 mhz selected cm 5 =0 (x in oscillating) cm 4 =0 (32 khz stopped) cm 3 =1 (x cout drivability high) double-speed mode ( f =6.3 mhz) cm 7 =1 double-speed mode cm 6 =1 6.3 mhz selected cm 5 =0 (x in oscillating) cm 4 =0 (32 khz stopped) cm 3 =1 (x cout drivability high) middle-speed mode ( f =788 khz) cm 7 =0 middle-speed mode cm 6 =1 6.3 mhz selected cm 5 =0 (x in oscillating) cm 4 =1 (32 khz oscillating) cm 3 =1 (x cout drivability high) double-speed mode ( f =6.3 mhz) cm 7 =1 double-speed mode cm 6 =1 6.3 mhz selected cm 5 =0 (x in oscillating) cm 4 =1 (32 khz oscillating) cm 3 =1 (x cout drivability high) high-speed mode ( f =3.15 mhz) cm 7 =0 high-speed mode cm 6 =0 6.3 mhz selected cm 5 =0 (x in oscillating) cm 4 =1 (32 khz oscillating) cm 3 =1 (x cout drivability high) low-speed mode ( f =16 khz) cm 7 =1 low-speed mode cm 6 =0 32 khz selected cm 5 =0 (x in oscillating) cm 4 =1 (32 khz oscillating) cm 3 =0 (x cout drivability low) low-speed mode ( f =16 khz) cm 7 =1 low-speed mode cm 6 =0 32 khz selected cm 5 =0 (x in oscillating) cm 4 =1 (32 khz oscillating) cm 3 =1 (x cout drivability high) low-speed mode ( f =16 khz) cm 7 =1 low consumption mode cm 6 =0 32 khz selected cm 5 =1 (x in stopped) cm 4 =1 (32 khz oscillating) cm 3 =0 (x cout drivability low) cm 3 : x cout drivability selection bit 0 : low 1 : high cm 4 : port xc switch bit 0 : i/o port function 1 : x cin -x cout oscillating function cm 5 : main clock (x in - x out ) stop bit 0 : oscillating 1 : stopped cm 7 ,cm 6 : main clock division ratio selection bits cm 7 cm 6 0 0 : f =f(x in )/2 (high-speed mode) 0 1 : f =f(x in )/8 (middle-speed mode) 1 0 : f =f(x cin )/2 (low-speed mode) 1 1 : f =f(x in ) (double-speed mode) cpu mode register (cpum: address 003b 16 ) cm 3 0 ? 1 cm 5 0 ? 1 cm 5 1 ? 0 cm 3 0 ? 1 cm 6 0 1 0 ? 1 cm 7 1 ? 0 0 ? 1 cm 7 0 ? 1 cm 7 0 ? 1 cm 6 0 ? 1 0 ? 1 cm 7 1 ? 0 cm 7 0 ? 1 0 ? 1 cm 7 1 ? 0 0 ? 1 cm 4 1 ? 0 cm 7 0 ? 1 cm 7 cm 4 0 ? 1 cm 4 1 ? 0 cm 4 1 ? 0 cm 4 1 ? 0 cm 7 0 ? 1 cm 6 0 ? 1 0 ? 1 cm 7 0 ? 1 cm 4 1 ? 0 cm 0 0 ? 1 0 ? 1 cm 6 cm 4 0 ? 1 b7 b0 cm 6 cm 6 cm 6 cm 3 cm 6 cm 3 65 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before performing a bbc or bbs instruction. interrupt source determination ? use ldm, sta, etc., instructions to clear interrupt request bits assigned to the interrupt source determination register 1, the in- terrupt source determination register 2, the transmit status register, or the receive status register. (do not use read-modify- write instructions such as clb, seb, etc. use the ldm or sta instruction to clear these bits.) ? request bits of interrupt source determination registers are not automatically cleared when an interrupt occurs. after an inter- rupt source has been determined, and before execution of the rti or cli instruction, the user must clear the bit by program. (use the ldm or sta instruction to clear.) ? the interrupt assigned to the interrupt source determination reg- isters occur 1 instruction execution later than a normal interrupt. the maximum timing is 16 machine cycles in the mul, div in- structions. decimal calculations ? to calculate in decimal notation, set the decimal mode flag (d) to 1, then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. ? in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers if a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n+1). multiplication and division instructions ? the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. ? the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer instruction (lda, etc.) ? the operation instruction when the index x mode flag (t) is 1 ? the addressing mode which uses the value of a direction regis- ter as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. serial i/o1 ? in clock synchronous serial i/o, if the receive side is using an external clock and it is to output the s rdy1 signal, set the trans- mit enable bit, the receive enable bit, and the s rdy output enable bit to 1. serial i/o1 continues to output the final bit from the t x d pin af- ter transmission is completed. ? in order to stop a transmit, set the transmit enable bit to 0 (transmit disable). do not set only the serial i/o1 enable bit to 0. ? a receive operation can be stopped by either setting the receive enable bit to 0 or the serial i/o1 enable bit to 0. ? to stop a transmit when transferring in clock synchronous serial i/o mode, set both the transmit enable bit and the receive en- able bit to 0 at the same time. ? to set the serial i/o1 control register again, first set the transmit enable/receive enable bits to 0. next, reset the transmit/re- ceive circuits, and, finally, reset the serial i/o1 control register. ? note when confirming the transmit shift register completion flag and controlling the data transmit after writing a transmit data to the transmit buffer. there is a delay of 0.5 to 1.5 shift clock cycles while the transmit shift register completion flag goes from 1 to 0. 66 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers serial i/o3 ? when writing 1 to the serial i/o initialization bit of the serial i/o3 control register 1, serial i/o3 is enabled, but each register is not initialized. set the value of each register by program. ? a serial i/o3 interrupt request occurs when 0 is written to the serial i/o initialization bit during an operation in automatic trans- fer serial i/o mode. disable the interrupt enable bit as necessary by program. a-d converter/d-a converter ? the a-d/d-a conversion register functions as an a-d conversion register during a read and a d-a conversion during a write. ac- cordingly, the d-a conversion register set value cannot be read out. ? the comparator for a-d converter uses capacitive coupling am- plifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(x in ) is at least on 500 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d con- version. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock f by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. the frequency of the internal clock f is half of the x in frequency. data link layer communication control ? the data link layer communication control circuit stops after a reset. to restart or change modes, write 00xxxxx1 2 to the communication mode register. note that bits 4 and 5 are read- only bits. ? the p7 5 /bus out pin operates as a general-purpose pin after release from reset. as a general-purpose port, its input/output can be switched by the direction register. clock changes ? use the ldm, sta, etc. instructions to modify the division ratio of internal system clock f . (do not use read-modify-write instruc- tions such as clb, seb, etc.) ? do not modify the division ratio of the internal system clock until the mode has been changed. for details concerning the number of cycles necessary to change modes, refer to the clock section in the explanation of about function blocks. ? use the ldm, sta, etc., instructions to clear interrupt request bits assigned to the interrupt source determination register 1, the interrupt source determination register 2, the transmit status register, or the receive status register. (do not use read-modify- write instructions such as clb, seb, etc.) ? before executing the cli or rti instruction during an interrupt processing routine, use the ldm or sta instruction to clear the interrupt request bits of interrupt source determination registers which have completed the interrupt processing. ? if switching the mode between low-speed and double-speed, switch the mode to middle/high-speed first, and then switch the mode to double-speed by program. do not switch the mode from low-speed to double-speed directly. 1 to 4 machine cycles are required for switching from low-speed mode to other mode. insert clock switch timing wait for switching the mode to middle/high-speed, and then switch the mode to double-speed. table 8 lists the recommended transition process for system clock switch. figure 72 shows the program example. table 8 clock switch combination recommended transition process low-speed ? high-speed low-speed ? middle-speed double-speed ? high-speed double-speed ? middle-speed double-speed ? low-speed middle-speed ? high-speed middle-speed ? middle-speed middle-speed ? low-speed high-speed ? double-speed high-speed ? middle-speed high-speed ? low-speed fig. 72 program example low-speed mode middle/high-speed mode double-speed mode switch ldm xx, cpum ?ow-speed mode middle/high-speed mode switch nop clock switch timing wait nop (1 to 4 machine cycles are required for switching mode.) ldm yy, cpum ?witch mode to double-speed note: cpum = cpu mode register (address 003b 16 ) 67 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom order confirmation form 2.mark specification form 3.data to be written to rom, in eprom form (three identical cop- ies) data required for rom writing orders the following are necessary when ordering a rom writing: 1.rom writing confirmation form 2.mark specification form 3.data to be written to rom, in eprom form (three identical cop- ies) rom programming method the prom of the blank one time prom version is not tested or screened in the assembly process and following processes. to en- sure proper operation after programming, the procedure shown in figure 73 is recommended to verify programming. fig. 73 programming and testing of one time prom version programming with prom programmer screening (caution) (150 c for 40 hours) verification with prom programmer functional check in target device the screening temperature is far higher than the storage temperature. never expose to 150 c exceeding 100 hours. caution : 68 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers h input voltage reset, x in v cc power source voltage v 4.0 electrical characteristics table 9 absolute maximum ratings (extended operating temperature version and automotive version) v cc power source voltage input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , v ref input voltage reset, x in input voltage p9 7 output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , x out C0.3 to 7.0 v all voltages are based on vss. output transis- tors are cut off. symbol parameter conditions ratings unit symbol power source voltage table 10 recommended operating conditions (extended operating temperature version and automotive version, vcc = 3.0 to 5.5 v, ta = C40 to 85c, unless otherwise noted) parameter at operating data link layer communication control circuit 5.0 5.5 unit min. typ. max. ta = 25c v ss v ref av ss v ia v ih v ih v il v il v il double-speed mode high-speed mode middle-speed mode low-speed mode analog reference voltage (when a-d converter is used) analog reference voltage (when d-a converter is used) h input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 7 l input voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 , p9 7 l input voltage reset 4.0 4.0 3.0 3.0 2.0 3.0 av ss 0.8v cc 0.8v cc 0 0 0 5.0 5.0 5.0 5.0 0 0 5.5 5.5 5.5 5.5 v cc v cc v cc v cc v cc 0.2v cc 0.2v cc 0.16v cc v v v v v v v v v v v v v v v i v i v i v o p d t opr t stg C0.3 to vcc +0.3 C0.3 to vcc +0.3 C0.3 to vcc +0.3 C0.3 to vcc +0.3 500 C40 to 85 C60 to 150 v v v v mw c c power source voltage power dissipation operating temperature storage temperature analog power source voltage analog input voltage an 0 to an 7 l input voltage x in 69 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers limits unit h total peak output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 h total peak output current p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 l total peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 l total peak output current p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 h total average output current (note 1) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 h total average output current p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 l total average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p8 0 Cp8 7 l total average output current p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 ma ma ma ma ma ma ma ma ma ma ma ma mhz mhz khz symbol table 11 recommended operating conditions (1) (extended operating temperature version and automotive version, vcc = 3.0 to 5.5 v, ta = C40 to 85c, unless otherwise noted) parameter s i oh(peak) s i oh(peak) s i ol(peak) s i ol(peak) s i oh(avg) s i oh(avg) s i ol(avg) s i ol(avg) i oh(peak) i ol(peak) i oh(avg) i ol(avg) C 80 C 80 80 80 C 40 C 40 40 40 C 10 10 C 5.0 5.0 2.5 6.4 50 min. ty p. max. 32.768 notes 1: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value mea- sured over 100 ms. the total peak current is the peak value of all the currents. 2: the peak output current is the peak current flowing in each port. 3: the average output current i ol(avg) , i oh(avg) in an average value measured over 100 ms. 4: choose an external oscillator which ensures no warps in the oscillation waveform as well as sufficient amplitude for the main c lock oscillation cir- cuit. use according to the manufacturers recommended conditions. mhz mhz mhz unit main clock input oscillation frequency symbol limits parameter min. typ. max. high-speed mode/middle-speed mode double-speed mode (4.0 v cc < 4.5v) double-speed mode (4.5 v cc 5.5v) 6.4 2.8v cc C 6.2 6.4 f(x in ) table 12 recommended operating conditions (2) (when rom/prom size is 60 kbytes) (vcc = 3.0 to 5.5 v, ta = C40 to 85c, unless otherwise noted) note 5: when using the microcomputer in the low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in )/3. h peak output current (note 2) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 l peak output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 h average output current (note 3) p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 l average output current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) timer x, timer y input oscillation frequency (at duty cycle of 50%) main clock input oscillation frequency (note 4) sub-clock input oscillation frequency (notes 4, 5) 70 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers v v oh h output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p8 0 Cp8 7 (note) l output voltage p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 hysteresis int 0 Cint 5 , adt, cntr 0 , cntr 1 symbol limits table 13 electrical characteristics (extended operating temperature version and automotive version, vcc = 4.0 to 5.5 v, vss = 0 v, ta = C40 to 85c, unless otherwi se noted) parameter unit min. typ. max. test conditions valid hysteresis only when these pins is used as the function v cc C 2.0 v cc C 1.0 2.0 0.5 5.0 note: when p4 5 /txd, p7 1 /s out2 , and p7 2 /s clk2 are cmos output states (when not p-channel output disable states) i oh = C 10 ma v cc = 4.0C5.5 v i oh = C 1 ma v cc = 3.0C5.5 v i ol = 10 ma v cc = 4.0C5.5 v i ol = 1.0 ma v cc = 3.0C5.5 v 2.0 1.0 hysteresis reset h input current p9 7 h input current reset h input current x in l input current p9 7 l input current reset l input current x in v ol v t + C v t C v t + C v t C v t + C v t C i ih i ih i ih i ih i il i il i il i il v i = v cc v i = v cc v i = v cc v i = v cc v i = v ss v i = v ss v i = v ss v i = v ss 0.5 0.5 4.0 C 4.0 5.0 5.0 C 5.0 C 5.0 C 5.0 5.5 v v v v v v m a m a m a m a m a m a m a m a v hysteresis r x d, s clk1 , s in2 , s clk2 , p2 0 Cp2 7 h input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 l input current p0 0 Cp0 7 , p1 0 Cp1 7 , p2 0 Cp2 7 , p3 0 Cp3 7 , p4 0 Cp4 7 , p5 0 Cp5 7 , p6 0 Cp6 7 , p7 0 Cp7 7 , p8 0 Cp8 7 when clock stopped ram hold voltage v ram 71 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers symbol limits table 14 electrical characteristics (extended operating temperature version and automotive version, vcc = 4.0 to 5.5 v, vss = 0 v, ta = C40 to 85c, unless otherwi se noted) parameter unit min. typ. max. test conditions double-speed mode, at operating data link layer communication control circuit f(x in ) = 6.29 mhz f(x cin ) = 32 khz output transistors off during a-d conversion double-speed mode, at stopping data link layer communication control circuit f(x in ) = 6.29 mhz f(x cin ) = 32 khz output transistors off during a-d conversion double-speed mode, at stopping data link layer communication control circuit f(x in ) = 6.29 mhz (in wit state) f(x cin ) = 32 khz output transistors off during a-d conversion high-speed mode, at operating data link layer communication control circuit f(x in ) = 6.29 mhz f(x cin ) = 32 khz output transistors off during a-d conversion high-speed mode, at stopping data link layer communication control circuit f(x in ) = 6.29 mhz f(x cin ) = 32 khz output transistors off during a-d conversion high-speed mode, at stopping data link layer communication control circuit f(x in ) = 6.29 mhz (in wit state) f(x cin ) = 32 khz output transistors off during a-d conversion low-speed mode (v cc = 3.0 v) f(x in ) = stopped f(x cin ) = 32 khz low power dissipation mode (cm 5 = 0) output transistors off low-speed mode (v cc = 3.0 v) f(x in ) = stopped f(x cin ) = 32 khz (in wit state) low power dissipation mode (cm 5 = 0) output transistors off all oscillation stopped (in stp state) output transistors off ta = 25c (note) 18.0 24.0 ma note: the a-d conversion is inactive. (the aCd conversion complete.) v ref current is not included. i cc power source current ta = 85c (note) 12.0 2.0 12.0 8.0 2.0 60 20 0.1 18.0 3.5 19.0 12.0 3.5 200 40 1.0 10 ma ma ma ma ma m a m a m a m a 72 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers bits lsb tc( f ) k w m a m a resolution absolute accuracy (excluding quantization error) conversion time ladder resistor reference power source input current analog port input current min. 12 50 ty p. 1 35 150 0.5 max. 8 2.5 50 100 200 5.0 v ref = 5.0 v table 15 a-d converter characteristics (extended operating temperature version and automotive version, v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, v ref = 2.0 v to v cc , ta = C40 to 85c, unless otherwise noted) unit limits parameter C C t conv r ladder i vref i i(ad) test conditions table 16 d-a converter characteristics (extended operating temperature version and automotive version, v cc = 4.0 to 5.5 v, v ss = av ss = 0 v, v ref = 2.0 v to v cc , ta = C40 to 85c, unless otherwise noted) symbol bits % m s k w ma resolution absolute accuracy setting time output resistor reference power source input current min. 1 ty p. 2.5 max. 8 1.0 3.0 4.0 3.2 unit limits parameter C C tsu ro i vref test conditions symbol 73 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers timing requirements table 17 timing requirements (extended operating temperature version and automotive version, v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C40 to 85c, unless otherwise noted) reset input l pulse width external clock input cycle time external clock input h pulse width external clock input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width int 0 to int 5 input h pulse width cntr 0 , cntr 1 input l pulse width int 0 to int 5 input l pulse width serial i/o1 clock input cycle time (note) t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr) t wh (cntr) t wh (int) t wl (cntr) t wl (int) t c (s clk1 ) t c (s clk2 ) t c (s clk3 ) t wh (s clk1 ) t wh (s clk2 ) limits m s ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 159 63 63 200 80 80 80 80 800 1000 1000 370 400 typ. max. symbol unit note : when bit 6 of address 001a 16 is 1 (clock synchronous). divide this value by four when bit 6 of address 001a 16 is 0 (uart). t wh (s clk3 ) t wl (s clk1 ) t wl (s clk2 ) t wl (s clk3 ) t su (r x d-s clk1 ) t su (s in2 -s clk2 ) t su (r in3 -s clk3 ) t h (s clk1 -r x d) t h (s clk2 -s in2 ) t h (s clk3 -s in3 ) serial i/o3 clock input h pulse width serial i/o1 clock input l pulse width (note) serial i/o2 clock input l pulse width serial i/o3 clock input l pulse width serial i/o1 input setup time serial i/o2 input setup time serial i/o3 input setup time serial i/o1 input hold time serial i/o2 input hold time serial i/o3 input hold time serial i/o2 clock input cycle time serial i/o3 clock input cycle time serial i/o1 clock input h pulse width (note) serial i/o2 clock input h pulse width ns ns ns ns ns ns ns ns ns ns 400 370 400 400 220 200 200 100 200 200 74 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers max. 140 140 140 table 18 switching characteristics (extended operating temperature version and automotive version, v cc = 4.0 to 5.5 v, v ss = 0 v, ta = C40 to 85c, unless otherwise noted) serial i/o1 clock output h pulse width serial i/o2 clock output h pulse width (note 1) serial i/o3 clock output h pulse width (note 5) serial i/o1 clock output l pulse width serial i/o2 clock output l pulse width (note 1) serial i/o3 clock output l pulse width (note 5) serial i/o1 output delay time (note 3) serial i/o2 output delay time (notes 1, 2) serial i/o3 output delay time (notes 5, 6) serial i/o1 output valid time (note 3) serial i/o2 output valid time (notes 1, 2) serial i/o3 output valid time (notes 5, 6) t wh (s clk1 ) t wh (s clk2 ) t wh (s clk3 ) t wl (s clk1 ) t wl (s clk2 ) t wl (s clk3 ) t d (s clk1 -t x d) t d (s clk2 -s out2 ) t d (s clk3 -s out3 ) t v (s clk1 -t x d) t v (s clk2 -s out2 ) limits ns ns ns ns ns ns ns ns ns ns ns ns parameter min. t c (s clk1 )/2C30 t c (s clk2 )/2C30 t c (s clk3 )/2C30 t c (s clk1 )/2C30 t c (s clk2 )/2C30 t c (s clk3 )/2C30 C30 0 0 ty p . symbol unit t v (s clk3 -s out3 ) t r (s clk1 ) t f (s clk1 ) t r (s clk2 ) t f (s clk2 ) t r (s clk3 ) t f (s clk3 ) serial i/o1 clock output rising time serial i/o1 clock output falling time serial i/o2 clock output rising time (note 1) serial i/o2 clock output falling time (note 1) serial i/o3 clock output rising time (note 5) serial i/o3 clock output falling time (note 5) cmos output rising time (note 4) cmos output falling time (note 4) t r (cmos) t f (cmos) notes 1: when p7 2 /s clk2 is cmos output. 2: when p7 1 /s out2 is cmos output. 3: when p4 5 /t x d is cmos output. 4: the x out pin is excluded. 5: when p8 4 /s clk3 is cmos output. 6: when p8 2 /s out3 is cmos output. 10 10 10 10 10 10 10 10 30 30 30 30 30 30 30 30 ns ns ns ns ns ns ns ns 75 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 74 circuit for measuring output switching characteristics cmos output measurement output pin 100 pf 76 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers fig. 75 timing diagram (in single-chip mode) timing diagram 0.2v cc t wl(int) 0.8v cc t wh(int) 0.2v cc 0.2v cc 0.8v cc 0.8v cc 0.16v cc t wl(x in ) 0.8v cc t wh(x in) t c(x in ) x in 0.2v cc 0.8v cc t w(reset) reset t f t r 0.2v cc t wl(cntr) 0.8v cc t wh(cntr) t c(cntr) t d(s clk1 -t x d) ,t d(s clk2- s out2 ) ,t d(s clk3- s out3 ) t v(s clk1 -t x d), t v(s clk2- s out2 ), t v(s clk3- s out3 ) t c(s clk1 ), t c(s clk2 ), t c(s clk3 ) t wl(s clk1 ), t wl(s clk2 ), t wl(s clk3 ) t wh(s clk1 ), t wh(s clk2 ), t wh(s clk3 ) t h (s clk1- r x d), t h (s clk2- s in 2), t h (s clk3- s in 3) t su(r x d - s clk1 ), t su(s in2- s clk2 ), t su(s in3- s clk3 ) t x d s out2 s out3 r x d s in2 s in3 s clk1 s clk2 s clk3 77 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers gzz-sh52-76b<84a0> receipt 740 family mask rom confirmation form single-chip microcomputer m38747m4t-xxxgp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address c080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38747m4tC must be entered in addresses 0000 16 to 0009 16 . and set the data ff 16 in addresses 000a 16 to 000f 16 . ascii codes and addresses are listed to the next page. (3) addresses 0010 16 to 001f 16 are ascii codes reserved area of sub rom number for the data link layer communication control circuit. write ascii codes of sub rom number for the data link layer communication control circuit, which has been used at developing the submitted rom, to addresses 0010 16 to 001f 16 of eprom certainly. refer to ascii codes of the next page at writing. eprom type (indicate the type used) sub rom number of data link laye r communication control circuit 27512 27101 0000 16 000f 16 0010 16 001f 16 0020 16 c07f 16 c080 16 fffd 16 fffe 16 ffff 16 eprom address eprom address product name ascii code : m38747m4tC data rom 16k-130 bytes sub rom number ascii code 0000 16 000f 16 0010 16 001f 16 0020 16 c07f 16 c080 16 fffd 16 fffe 16 1ffff 16 product name ascii code : m38747m4tC data rom 16k-130 bytes sub rom number ascii code (1/3) 78 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 740 family mask rom confirmation form single-chip microcomputer m38747m4t-xxxgp mitsubishi electric gzz-sh52-76b<84a0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembier source program because ascii codes of the product name are written to addresses 0000 16 to 0009 16 of eprom. ascii codes of sub rom number are written to addresses 0010 16 to 0017 16 by using the pseudo-command in the same way. 27512 27101 eprom type the pseudo-command *= d $0000 .byte d m38747m4tC *= d $0000 .byte d m38747m4tC note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. (2/3) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (80p6s) and attach it to the mask rom confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = ceramic resonator external clock input quartz crystal other ( ) mhz address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 7 = 37 16 4 = 34 16 7 = 37 16 m = 4d 16 4 = 34 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t =54 16 - =2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ascii codes 0 =30 16 1 =31 16 2 =32 16 3 =33 16 4 =34 16 5 =35 16 6 =36 16 7 =37 16 8 =38 16 9 =39 16 a =41 16 b =42 16 c =43 16 d =44 16 e =45 16 f =46 16 g =38 16 h =39 16 k =4b 16 l =4c 16 m =4d 16 n =4e 16 p =50 16 q =51 16 r =52 16 s =53 16 t =54 16 u =55 16 v =56 16 w =57 16 x =58 16 y =59 16 z =5a 16 (2) how will you use the x cin -x cout oscillator? ceramic resonator external clock input quartz crystal other ( ) not use (use for p4 0 ,p4 1 ) at what frequency? f(x c in ) = mhz (3) which clock division ratio will you use? (possible to select plural) f = x in (double-speed mode) f = x in /2 (high-speed mode) f = x in /8 (middle-speed mode) f = x c in /2 (low-speed mode) 79 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers gzz-sh52-76b<84a0> 740 family mask rom confirmation form single-chip microcomputer m38747m4t-xxxgp mitsubishi electric mask rom number (3/3) (4) will you use the data link layer communication control circuit? yes no h 4. comments 80 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers gzz-sh52-77b<84a0> receipt 740 family mask rom confirmation form single-chip microcomputer m38747m6t-xxxgp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address a080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38747m6tC must be entered in addresses 0000 16 to 0009 16 . and set the data ff 16 in addresses 000a 16 to 000f 16 . ascii codes and addresses are listed to the next page. (3) addresses 0010 16 to 001f 16 are ascii codes reserved area of sub rom number for the data link layer communication control circuit. write ascii codes of sub rom number for the data link layer communication control circuit, which has been used at developing the submitted rom, to addresses 0010 16 to 001f 16 of eprom certainly. refer to ascii codes of the next page at writing. (1/3) eprom type (indicate the type used) sub rom number of data link laye r communication control circuit 27512 27101 0000 16 000f 16 0010 16 001f 16 0020 16 a07f 16 a080 16 fffd 16 fffe 16 ffff 16 eprom address eprom address product name ascii code : m38747m6tC data rom 24k-130 bytes sub rom number ascii code 0000 16 000f 16 0010 16 001f 16 0020 16 a07f 16 a080 16 fffd 16 fffe 16 1ffff 16 product name ascii code : m38747m6tC data rom 24k-130 bytes sub rom number ascii code 81 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 740 family mask rom confirmation form single-chip microcomputer m38747m6t-xxxgp mitsubishi electric gzz-sh52-77b<84a0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembier source program because ascii codes of the product name are written to addresses 0000 16 to 0009 16 of eprom. ascii codes of sub rom number are written to addresses 0010 16 to 0017 16 by using the pseudo-command in the same way. 27512 27101 eprom type the pseudo-command *= d $0000 .byte d m38747m6tC *= d $0000 .byte d m38747m6tC note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. (2/3) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (80p6s) and attach it to the mask rom confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = ceramic resonator external clock input quartz crystal other ( ) mhz address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 7 = 37 16 4 = 34 16 7 = 37 16 m = 4d 16 6 = 36 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t =54 16 - =2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ascii codes 0 =30 16 1 =31 16 2 =32 16 3 =33 16 4 =34 16 5 =35 16 6 =36 16 7 =37 16 8 =38 16 9 =39 16 a =41 16 b =42 16 c =43 16 d =44 16 e =45 16 f =46 16 g =38 16 h =39 16 k =4b 16 l =4c 16 m =4d 16 n =4e 16 p =50 16 q =51 16 r =52 16 s =53 16 t =54 16 u =55 16 v =56 16 w =57 16 x =58 16 y =59 16 z =5a 16 (2) how will you use the x cin -x cout oscillator? ceramic resonator external clock input quartz crystal other ( ) not use (use for p4 0 ,p4 1 ) at what frequency? f(x c in ) = mhz (3) which clock division ratio will you use? (possible to select plural) f = x in (double-speed mode) f = x in /2 (high-speed mode) f = x in /8 (middle-speed mode) f = x c in /2 (low-speed mode) 82 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers gzz-sh52-77b<84a0> 740 family mask rom confirmation form single-chip microcomputer m38747m6t-xxxgp mitsubishi electric mask rom number (3/3) (4) will you use the data link layer communication control circuit? yes no h 4. comments 83 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers gzz-sh52-75b<84a0> receipt 740 family mask rom confirmation form single-chip microcomputer m38747mct-xxxgp mitsubishi electric mask rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce masks based on this data. we shall assume the responsibility for errors only if the mask rom data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address 4080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38747mctC must be entered in addresses 0000 16 to 0009 16 . and set the data ff 16 in addresses 000a 16 to 000f 16 . ascii codes and addresses are listed to the next page. (3) addresses 0010 16 to 001f 16 are ascii codes reserved area of sub rom number for the data link layer communication control circuit. write ascii codes of sub rom number for the data link layer communication control circuit, which has been used at developing the submitted rom, to addresses 0010 16 to 001f 16 of eprom certainly. refer to ascii codes of the next page at writing. (1/3) eprom type (indicate the type used) sub rom number of data link laye r communication control circuit 27512 27101 0000 16 000f 16 0010 16 001f 16 0020 16 407f 16 4080 16 fffd 16 fffe 16 ffff 16 eprom address eprom address product name ascii code : m38747mctC data rom 48k-130 bytes sub rom number ascii code 0000 16 000f 16 0010 16 001f 16 0020 16 407f 16 4080 16 fffd 16 fffe 16 1ffff 16 product name ascii code : m38747mctC data rom 48k-130 bytes sub rom number ascii code 84 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 740 family mask rom confirmation form single-chip microcomputer m38747mct-xxxgp mitsubishi electric gzz-sh52-75b<84a0> mask rom number we recommend the use of the following pseudo-command to set the start address of the assembier source program because ascii codes of the product name are written to addresses 0000 16 to 0009 16 of eprom. ascii codes of sub rom number are written to addresses 0010 16 to 0017 16 by using the pseudo-command in the same way. 27512 27101 eprom type the pseudo-command *= d $0000 .byte d m38747mctC *= d $0000 .byte d m38747mctC note : if the name of the product written to the eproms does not match the name of the mask confirmation form, the rom will not be processed. (2/3) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (80p6s) and attach it to the mask rom confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = ceramic resonator external clock input quartz crystal other ( ) mhz address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 7 = 37 16 4 = 34 16 7 = 37 16 m = 4d 16 c = 43 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t =54 16 - =2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ascii codes 0 =30 16 1 =31 16 2 =32 16 3 =33 16 4 =34 16 5 =35 16 6 =36 16 7 =37 16 8 =38 16 9 =39 16 a =41 16 b =42 16 c =43 16 d =44 16 e =45 16 f =46 16 g =38 16 h =39 16 k =4b 16 l =4c 16 m =4d 16 n =4e 16 p =50 16 q =51 16 r =52 16 s =53 16 t =54 16 u =55 16 v =56 16 w =57 16 x =58 16 y =59 16 z =5a 16 (2) how will you use the x cin -x cout oscillator? ceramic resonator external clock input quartz crystal other ( ) not use (use for p4 0 ,p4 1 ) at what frequency? f(x c in ) = mhz (3) which clock division ratio will you use? (possible to select plural) f = x in (double-speed mode) f = x in /2 (high-speed mode) f = x in /8 (middle-speed mode) f = x c in /2 (low-speed mode) 85 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers gzz-sh52-75b<84a0> 740 family mask rom confirmation form single-chip microcomputer m38747mct-xxxgp mitsubishi electric mask rom number (3/3) (4) will you use the data link layer communication control circuit? yes no h 4. comments 86 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers gzz-sh52-78b<84a0> receipt 740 family rom programming confirmation form single-chip microcomputer m38749eft-xxxgp mitsubishi electric rom number date: section head signature supervisor signature company name note : please fill in all items marked h . customer h issuance signature date issued submitted by tel () date: supervisor h 1. confirmation specify the name of the product being ordered and the type of eproms submitted. three eproms are required for each pattern. if at least two of the three sets of eproms submitted contain identical data, we will produce rom programming based on this data. we shall assume the responsibility for errors only if the rom programming data on the products we produce differs from this data. thus, extreme care must be taken to verify the data in the submitted eproms. checksum code for entire eprom (hexadecimal notation) in the address space of the microcomputer, the internal rom area is from address 1080 16 to fffd 16 . the reset vector is stored in addresses fffc 16 and fffd 16 . (1) set the data in the unused area (the shaded area of the diagram) to ff 16 . (2) the ascii codes of the product name m38749eftC must be entered in addresses 0000 16 to 0009 16 . and set the data ff 16 in addresses 000a 16 to 000f 16 . the ascii codes and addresses are listed to the next page. (1/3) eprom type (indicate the type used) sub rom number of data link laye r communication control circuit 27512 27101 0000 16 000f 16 0010 16 001f 16 0020 16 107f 16 1080 16 fffd 16 fffe 16 ffff 16 eprom address eprom address product name ascii code : m38749eftC data rom 60k-130 bytes sub rom number ascii code 0000 16 000f 16 0010 16 001f 16 0020 16 107f 16 1080 16 fffd 16 fffe 16 1ffff 16 product name ascii code : m38749eftC data rom 60k-130 bytes sub rom number ascii code (3) addresses 0010 16 to 001f 16 are ascii codes reserved area of sub rom number for the data link layer communication control circuit. write ascii codes of sub rom number for the data link layer communication control circuit, which has been used at developing the submitted rom, to addresses 0010 16 to 001f 16 of eprom certainly. refer to ascii codes of the next page at writing. 87 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers 740 family rom programming confirmation form single-chip microcomputer m38749eft-xxxgp mitsubishi electric gzz-sh52-78b<84a0> rom number 27512 27101 eprom type the pseudo-command *= d $0000 .byte d m38749eftC *= d $0000 .byte d m38749eftC note : if the name of the product written to the eproms does not match the name of the rom programming confirmation form, the rom will not be processed. (2/3) h 2. mark specification mark specification must be submitted using the correct form for the package being ordered. fill out the appropriate mark specification form (80p6s) and attach it to the rom programming confirmation form. h 3. usage conditions please answer the following questions about usage for use in our product inspection : (1) how will you use the x in -x out oscillator? at what frequency? f(x in ) = ceramic resonator external clock input quartz crystal other ( ) mhz address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 m = 4d 16 3 = 33 16 8 = 38 16 7 = 37 16 4 = 34 16 9 = 39 16 e = 45 16 f = 46 16 address 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 t =54 16 - =2d 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 ascii codes 0 =30 16 1 =31 16 2 =32 16 3 =33 16 4 =34 16 5 =35 16 6 =36 16 7 =37 16 8 =38 16 9 =39 16 a =41 16 b =42 16 c =43 16 d =44 16 e =45 16 f =46 16 g =38 16 h =39 16 k =4b 16 l =4c 16 m =4d 16 n =4e 16 p =50 16 q =51 16 r =52 16 s =53 16 t =54 16 u =55 16 v =56 16 w =57 16 x =58 16 y =59 16 z =5a 16 (2) how will you use the x cin -x cout oscillator? ceramic resonator external clock input quartz crystal other ( ) not use (use for p4 0 ,p4 1 ) at what frequency? f(x c in ) = mhz (3) which clock division ratio will you use? (possible to select plural) f = x in (double-speed mode) f = x in /2 (high-speed mode) f = x in /8 (middle-speed mode) f = x c in /2 (low-speed mode) we recommend the use of the following pseudo-command to set the start address of the assembier source program because ascii codes of the product name are written to addresses 0000 16 to 0009 16 of eprom. ascii codes of sub rom number are written to addresses 0010 16 to 0017 16 by using the pseudo-command in the same way. 88 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers gzz-sh52-78b<84a0> 740 family rom programming confirmation form single-chip microcomputer m38749eft-xxxgp mitsubishi electric rom number (3/3) (4) will you use the data link layer communication control circuit? yes no h 4. comments 89 3874 gr oup single-chip 8-bit cmos microcomputer mitsubishi microcomputers customer? s p ar ts number note : the fonts and size of characters are standard mitsubishi typ e. mitsubishi ic catalog name notes 1 : the mark field should be written right aligned. 2 : the fonts and size of characters are standard mitsubishi type. 3 : customer? s par ts number can be up to 10 alphan u- meric characters for capital letters, hyphens, commas, periods and so on. 4 : if the mitsubishi logo is not required, check the box belo w . mitsubishi logo is not required 5 : the allocation of mitsubishi ic catalog name and mitsubishi product number is different on the pac kage o wing to the n umber of mitsubishi ic catalog name? s characters, and the requiring mitsubishi logo or not. 80p6s (80-pin qfp) mark specifica tion form 80p6d, 80p6q (80-pin fine-pitch qfp) mitsubishi ic catalog name please choose one of the marking types below (a, b, c), and enter the mitsubishi ic catalog name and the special mark (i f neede d). a. standard mitsubishi mark c. special mark required b . customer? s p ar ts number + mitsubishi ic catalog name mitsubishi ic catalog name mitsubishi ic catalog name notes 1 : i f special mark is to be printed, indicate the desired la y out of the mar k in the left figure . the lay out will be duplicated technically as close as possible. mitsubishi product number (6-digit, or 7-digit) and mask rom number (3-digit) are always marked for sorting the products. 2 : if special char acter fonts (e .g., customer? s tr ade mar k logo) must be used in special mark, check the box be- low . for the new special character fonts, a clean font origi- nal (ideally logo drawing) must be submitted. special character fonts required 1 80 61 40 60 41 21 20 mitsubishi product number (6-digit, or 7-digit) 1 80 61 40 60 41 21 20 1 80 61 40 60 41 21 20 90 3874 group single-chip 8-bit cmos microcomputer mitsubishi microcomputers qfp80-p-1414-0.65 1.11 weight(g) jedec code eiaj package code lead material alloy 42 80p6s-a plastic 80pin 14 5 14mm body qfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 i 2 1.3 m d 14.6 m e 14.6 10 0 0.1 1.4 0.8 0.6 0.4 17.1 16.8 16.5 17.1 16.8 16.5 0.65 14.2 14.0 13.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 80 61 40 60 41 21 20 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f weight(g) jedec code eiaj package code 80d0 glass seal 80pin qfn 25 40 80 65 41 64 24 1 1.2typ 0.6typ 0.8typ index 1.78typ 3.32max 0.8typ 1.2typ 0.8typ 0.5typ 12.0 0.15 15.6 0.2 21.0 0.2 18.4 0.15 ? 1998 mitsubishi electric corp. new publication, effective jun. 1998. specifications subject to change without notice. notes regarding these materials ? these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. ? mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, origina ting in the use of any product data, diagrams, charts or circuit application examples contained in these materials. ? all information contained in these materials, including product data, diagrams and charts, represent information on products a t the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers co ntact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. ? mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. ? the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. ? if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. ? please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. keep safety first in your circuit designs! ? mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. rev. rev. no. date 1.0 first edition 980602 revision description list 3874 group data sheet (1/1) revision description |
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